ternary-logic/CMOS, branch master

ternary-logic/CMOS, branch master Ternary logic gate schematics Old uncommitted changes 2016-12-15T03:26:29+00:00 Jed Barber jjbarber@y7mail.com 2016-12-15T03:26:29+00:00 76682bade38a8b2d58490ddbb80cb627a2b2ad1b

Constructed 3-input ANTIMAX, ANTIMIN gates 2014-03-02T07:27:25+00:00 Jed Barber jjbarber@y7mail.com 2014-03-02T07:27:25+00:00 d57729e84cf430dbbf90b11a8d8fe9b4904730f3

Added symbols for SUM and XOR gates 2014-02-10T07:59:43+00:00 Jed Barber jjbarber@y7mail.com 2014-02-10T07:59:43+00:00 3fd1b6fdea0ab69c736eb4775343c95a0a4a26f6

Removed placeholder sum circuit 2014-02-10T07:53:45+00:00 Jed Barber jjbarber@y7mail.com 2014-02-10T07:53:45+00:00 229aae96c3baad6f424b043c9ff9ce68331d9f1b

Fixed references to subcircuits 2014-02-10T07:50:31+00:00 Jed Barber jjbarber@y7mail.com 2014-02-10T07:50:31+00:00 17dcd072f9faa054d955775dbe555e90cb9a7759

Fixed SUM gate 2014-02-10T05:52:36+00:00 Jed Barber jjbarber@y7mail.com 2014-02-10T05:52:36+00:00 5f6888ca7786fd9713b0383b3f7ae2697ad5107b

Fixed XOR gate 2014-02-09T23:10:00+00:00 Jed Barber jjbarber@y7mail.com 2014-02-09T23:10:00+00:00 9ce10f3e9f74e3d5cf97cced0f01266189a095ee

Working, but inefficient, SUM gate constructed 2014-02-03T05:57:57+00:00 Jed Barber jjbarber@y7mail.com 2014-02-03T05:57:57+00:00 b7a4c18177c73cd9de206423ab732314adb66e77

Constructed SUM gate (not working) 2014-02-02T07:40:29+00:00 Jed Barber jjbarber@y7mail.com 2014-02-02T07:40:29+00:00 9ce11b8e92b2766304f06217bd0e523427e57c0e

Constructed XOR gate (not working) 2014-01-30T17:00:05+00:00 Jed Barber jjbarber@y7mail.com 2014-01-30T17:00:05+00:00 45d370d43ecae58895ebc35025afe60451627a2a