ternary-logic/simulated, branch master

ternary-logic/simulated, branch master Ternary logic gate schematics Old uncommitted changes 2016-12-15T03:26:29+00:00 Jed Barber jjbarber@y7mail.com 2016-12-15T03:26:29+00:00 76682bade38a8b2d58490ddbb80cb627a2b2ad1b

Corrected transistor count 2014-03-01T07:23:51+00:00 Jed Barber jjbarber@y7mail.com 2014-03-01T07:23:51+00:00 28bd9be19ddbd09af7dd83843f593bff8259644c

Fixed symbols that shouldn't indicate inversion 2014-02-13T14:20:09+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T14:20:09+00:00 a4b044d8161034a286474464c3962b5200574536

Added symbols for the rest of the gates 2014-02-13T14:16:25+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T14:16:25+00:00 bc6c41ce7523e56688bf52f7ddeadb3b9785c602

Constructed simulated ternary SUM gate 2014-02-13T13:57:24+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T13:57:24+00:00 779850bf1cb8b3bc2156f594c29a0cb3a65cd03a

Constructed simulated ternary XOR gate 2014-02-13T13:36:36+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T13:36:36+00:00 eaa9f4d86ab2a7b346b0ed9f1e474ba19e23597f

Constructed simulated ternary EQUALITY gate 2014-02-13T13:36:20+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T13:36:20+00:00 7b1cc49a29825f8875026027e1ae2f44cf009337

Removed superfluous ground connections to AND/OR/NOT gates 2014-02-13T11:06:11+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T11:06:11+00:00 2f225c34b948344052bab408fd5fb2aac8985fef

Constructed simulated ternary GULLIBLE gate 2014-02-13T09:14:21+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T09:14:21+00:00 3e4a9e9163b71ccd340d12a54c29781dd89f7850

Constructed simulated ternary CONSENSUS gate 2014-02-13T08:23:44+00:00 Jed Barber jjbarber@y7mail.com 2014-02-13T08:23:44+00:00 3da3c65493a84825ec49dc0f6a2fa00b83c95f4a