From 76682bade38a8b2d58490ddbb80cb627a2b2ad1b Mon Sep 17 00:00:00 2001 From: Jed Barber Date: Thu, 15 Dec 2016 14:26:29 +1100 Subject: Old uncommitted changes --- .gitignore | 12 +- CMOS/2_input_antimax.asc | 210 +++++------ CMOS/2_input_antimax.asy | 48 +-- CMOS/2_input_antimin.asc | 206 +++++------ CMOS/2_input_antimin.asy | 48 +-- CMOS/2_input_max.asc | 30 +- CMOS/2_input_max.asy | 44 +-- CMOS/2_input_min.asc | 30 +- CMOS/2_input_min.asy | 44 +-- CMOS/3_input_antimax.asc | 270 +++++++------- CMOS/3_input_antimin.asc | 274 +++++++------- CMOS/buffer.asc | 24 +- CMOS/buffer.asy | 34 +- CMOS/clamp_down.asc | 80 ++-- CMOS/clamp_down.asy | 40 +- CMOS/clamp_up.asc | 76 ++-- CMOS/clamp_up.asy | 40 +- CMOS/consensus.asc | 30 +- CMOS/consensus.asy | 44 +-- CMOS/custom.mos | 46 +-- CMOS/decrement.asc | 146 ++++---- CMOS/decrement.asy | 34 +- CMOS/equality.asc | 338 ++++++++--------- CMOS/equality.asy | 44 +-- CMOS/gullible.asc | 30 +- CMOS/gullible.asy | 44 +-- CMOS/increment.asc | 146 ++++---- CMOS/increment.asy | 34 +- CMOS/inverting_consensus.asc | 200 +++++----- CMOS/inverting_consensus.asy | 46 +-- CMOS/inverting_gullible.asc | 324 ++++++++-------- CMOS/inverting_gullible.asy | 46 +-- CMOS/is_false.asc | 20 +- CMOS/is_false.asy | 34 +- CMOS/is_true.asc | 24 +- CMOS/is_true.asy | 34 +- CMOS/is_unknown.asc | 134 +++---- CMOS/is_unknown.asy | 34 +- CMOS/monadic_decoder.asc | 160 ++++---- CMOS/monadic_decoder.asy | 56 +-- CMOS/negative_threshold_inverter.asc | 90 ++--- CMOS/negative_threshold_inverter.asy | 36 +- CMOS/positive_threshold_inverter.asc | 90 ++--- CMOS/positive_threshold_inverter.asy | 36 +- CMOS/standard_inverter.asc | 126 +++---- CMOS/standard_inverter.asy | 36 +- CMOS/sum.asc | 588 +++++++++++++++--------------- CMOS/sum.asy | 44 +-- CMOS/xor.asc | 350 +++++++++--------- CMOS/xor.asy | 44 +-- RMOS/antimax.asc | 148 ++++---- RMOS/antimax.asy | 48 +-- RMOS/antimin.asc | 148 ++++---- RMOS/antimin.asy | 48 +-- RMOS/buffer.asc | 24 +- RMOS/buffer.asy | 34 +- RMOS/clamp_down.asc | 120 +++--- RMOS/clamp_down.asy | 40 +- RMOS/clamp_up.asc | 120 +++--- RMOS/clamp_up.asy | 40 +- RMOS/consensus.asc | 30 +- RMOS/consensus.asy | 44 +-- RMOS/custom.mos | 46 +-- RMOS/decrement.asc | 118 +++--- RMOS/decrement.asy | 34 +- RMOS/equality.asc | 268 +++++++------- RMOS/equality.asy | 44 +-- RMOS/gullible.asc | 190 +++++----- RMOS/gullible.asy | 44 +-- RMOS/increment.asc | 120 +++--- RMOS/increment.asy | 34 +- RMOS/inverting_consensus.asc | 134 +++---- RMOS/inverting_consensus.asy | 46 +-- RMOS/is_false.asc | 86 ++--- RMOS/is_false.asy | 34 +- RMOS/is_true.asc | 24 +- RMOS/is_true.asy | 34 +- RMOS/is_unknown.asc | 120 +++--- RMOS/is_unknown.asy | 34 +- RMOS/max.asc | 30 +- RMOS/max.asy | 44 +-- RMOS/min.asc | 30 +- RMOS/min.asy | 44 +-- RMOS/negative_threshold_inverter.asc | 86 ++--- RMOS/negative_threshold_inverter.asy | 36 +- RMOS/positive_threshold_inverter.asc | 86 ++--- RMOS/positive_threshold_inverter.asy | 36 +- RMOS/standard_inverter.asc | 106 +++--- RMOS/standard_inverter.asy | 36 +- RMOS/sum.asc | 388 ++++++++++---------- RMOS/sum.asy | 44 +-- RMOS/xor.asc | 226 ++++++------ RMOS/xor.asy | 44 +-- simulated/2_input_max.asc | 62 ++-- simulated/2_input_max.asy | 82 ++--- simulated/2_input_min.asc | 62 ++-- simulated/2_input_min.asy | 82 ++--- simulated/buffer.asc | 26 +- simulated/buffer.asy | 62 ++-- simulated/clamp_down.asc | 32 +- simulated/clamp_down.asy | 66 ++-- simulated/clamp_up.asc | 32 +- simulated/clamp_up.asy | 66 ++-- simulated/consensus.asc | 62 ++-- simulated/consensus.asy | 82 ++--- simulated/decrement.asc | 54 +-- simulated/decrement.asy | 62 ++-- simulated/equality.asc | 102 +++--- simulated/equality.asy | 82 ++--- simulated/gullible.asc | 86 ++--- simulated/gullible.asy | 82 ++--- simulated/increment.asc | 54 +-- simulated/increment.asy | 62 ++-- simulated/is_false.asc | 38 +- simulated/is_false.asy | 62 ++-- simulated/is_true.asc | 38 +- simulated/is_true.asy | 62 ++-- simulated/is_unknown.asc | 34 +- simulated/is_unknown.asy | 62 ++-- simulated/negative_threshold_inverter.asc | 38 +- simulated/negative_threshold_inverter.asy | 64 ++-- simulated/positive_threshold_inverter.asc | 38 +- simulated/positive_threshold_inverter.asy | 64 ++-- simulated/standard_inverter.asc | 38 +- simulated/standard_inverter.asy | 64 ++-- simulated/sum.asc | 188 +++++----- simulated/sum.asy | 82 ++--- simulated/xor.asc | 118 +++--- simulated/xor.asy | 82 ++--- 129 files changed, 5430 insertions(+), 5430 deletions(-) diff --git a/.gitignore b/.gitignore index c63bc84..728f384 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,6 @@ - -# ignore files generated by LTspice simulations - -*.log -*.raw -*.net + +# ignore files generated by LTspice simulations + +*.log +*.raw +*.net diff --git a/CMOS/2_input_antimax.asc b/CMOS/2_input_antimax.asc index d74f80e..4675cc2 100644 --- a/CMOS/2_input_antimax.asc +++ b/CMOS/2_input_antimax.asc @@ -1,105 +1,105 @@ -Version 4 -SHEET 1 972 680 -WIRE -496 -192 -528 -192 -WIRE -96 -192 -416 -192 -WIRE -528 -160 -528 -192 -WIRE -96 -144 -96 -192 -WIRE -144 -128 -304 -128 -WIRE 384 -112 32 -112 -WIRE 624 -112 384 -112 -WIRE 752 -112 624 -112 -WIRE 528 -48 224 -48 -WIRE -96 -16 -96 -48 -WIRE 384 -16 384 -112 -WIRE 624 -16 624 -112 -WIRE -304 0 -304 -128 -WIRE -304 0 -416 0 -WIRE -144 0 -192 0 -WIRE 336 64 288 64 -WIRE 528 64 528 -48 -WIRE 576 64 528 64 -WIRE -96 128 -96 80 -WIRE 32 128 32 -112 -WIRE 32 128 -96 128 -WIRE -192 144 -192 0 -WIRE -192 144 -416 144 -WIRE 384 176 384 80 -WIRE 496 176 384 176 -WIRE 624 176 624 80 -WIRE 624 176 496 176 -WIRE -192 192 -192 144 -WIRE -48 192 -192 192 -WIRE 224 192 224 -48 -WIRE 224 192 -48 192 -WIRE 496 208 496 176 -WIRE -304 288 -304 0 -WIRE 288 288 288 64 -WIRE 288 288 -304 288 -WIRE 448 288 288 288 -WIRE 496 336 496 304 -WIRE -96 352 -96 128 -WIRE -96 352 -208 352 -WIRE 32 352 -96 352 -WIRE -208 400 -208 352 -WIRE 32 400 32 352 -WIRE 224 416 224 192 -WIRE 448 416 224 416 -WIRE -304 480 -304 288 -WIRE -256 480 -304 480 -WIRE -48 480 -48 192 -WIRE -16 480 -48 480 -WIRE 496 496 496 432 -WIRE -496 544 -528 544 -WIRE -208 544 -208 496 -WIRE -208 544 -416 544 -WIRE 32 544 32 496 -WIRE 32 544 -208 544 -WIRE -528 576 -528 544 -FLAG 496 496 0 -FLAG -528 576 0 -FLAG -528 -160 0 -FLAG -416 0 A -IOPIN -416 0 In -FLAG -416 144 B -IOPIN -416 144 In -FLAG 752 -112 Y -IOPIN 752 -112 Out -SYMBOL pmos -144 -48 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos -144 80 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL nmos -256 400 R0 -SYMATTR InstName M3 -SYMATTR Value N-ENH -SYMBOL nmos -16 400 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL nmos 336 -16 R0 -SYMATTR InstName M5 -SYMATTR Value N-DLOW -SYMBOL nmos 576 -16 R0 -SYMATTR InstName M6 -SYMATTR Value N-DLOW -SYMBOL pmos 448 208 R0 -SYMATTR InstName M7 -SYMATTR Value P-DLOW -SYMBOL pmos 448 336 R0 -SYMATTR InstName M8 -SYMATTR Value P-DLOW -SYMBOL voltage -400 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value 1 -SYMBOL voltage -400 544 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V4 -SYMATTR Value -1 -TEXT 328 -176 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 972 680 +WIRE -496 -192 -528 -192 +WIRE -96 -192 -416 -192 +WIRE -528 -160 -528 -192 +WIRE -96 -144 -96 -192 +WIRE -144 -128 -304 -128 +WIRE 384 -112 32 -112 +WIRE 624 -112 384 -112 +WIRE 752 -112 624 -112 +WIRE 528 -48 224 -48 +WIRE -96 -16 -96 -48 +WIRE 384 -16 384 -112 +WIRE 624 -16 624 -112 +WIRE -304 0 -304 -128 +WIRE -304 0 -416 0 +WIRE -144 0 -192 0 +WIRE 336 64 288 64 +WIRE 528 64 528 -48 +WIRE 576 64 528 64 +WIRE -96 128 -96 80 +WIRE 32 128 32 -112 +WIRE 32 128 -96 128 +WIRE -192 144 -192 0 +WIRE -192 144 -416 144 +WIRE 384 176 384 80 +WIRE 496 176 384 176 +WIRE 624 176 624 80 +WIRE 624 176 496 176 +WIRE -192 192 -192 144 +WIRE -48 192 -192 192 +WIRE 224 192 224 -48 +WIRE 224 192 -48 192 +WIRE 496 208 496 176 +WIRE -304 288 -304 0 +WIRE 288 288 288 64 +WIRE 288 288 -304 288 +WIRE 448 288 288 288 +WIRE 496 336 496 304 +WIRE -96 352 -96 128 +WIRE -96 352 -208 352 +WIRE 32 352 -96 352 +WIRE -208 400 -208 352 +WIRE 32 400 32 352 +WIRE 224 416 224 192 +WIRE 448 416 224 416 +WIRE -304 480 -304 288 +WIRE -256 480 -304 480 +WIRE -48 480 -48 192 +WIRE -16 480 -48 480 +WIRE 496 496 496 432 +WIRE -496 544 -528 544 +WIRE -208 544 -208 496 +WIRE -208 544 -416 544 +WIRE 32 544 32 496 +WIRE 32 544 -208 544 +WIRE -528 576 -528 544 +FLAG 496 496 0 +FLAG -528 576 0 +FLAG -528 -160 0 +FLAG -416 0 A +IOPIN -416 0 In +FLAG -416 144 B +IOPIN -416 144 In +FLAG 752 -112 Y +IOPIN 752 -112 Out +SYMBOL pmos -144 -48 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos -144 80 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL nmos -256 400 R0 +SYMATTR InstName M3 +SYMATTR Value N-ENH +SYMBOL nmos -16 400 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL nmos 336 -16 R0 +SYMATTR InstName M5 +SYMATTR Value N-DLOW +SYMBOL nmos 576 -16 R0 +SYMATTR InstName M6 +SYMATTR Value N-DLOW +SYMBOL pmos 448 208 R0 +SYMATTR InstName M7 +SYMATTR Value P-DLOW +SYMBOL pmos 448 336 R0 +SYMATTR InstName M8 +SYMATTR Value P-DLOW +SYMBOL voltage -400 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value 1 +SYMBOL voltage -400 544 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value -1 +TEXT 328 -176 Left 0 !.inc ./custom.mos diff --git a/CMOS/2_input_antimax.asy b/CMOS/2_input_antimax.asy index e29234c..8ef0d80 100644 --- a/CMOS/2_input_antimax.asy +++ b/CMOS/2_input_antimax.asy @@ -1,24 +1,24 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 56 48 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 77 Center 0 MAX -TEXT 0 52 Center 0 ANTI -SYMATTR Description 2-input ANTIMAX gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 77 Center 0 MAX +TEXT 0 52 Center 0 ANTI +SYMATTR Description 2-input ANTIMAX gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/2_input_antimin.asc b/CMOS/2_input_antimin.asc index 14b61d2..79255dc 100644 --- a/CMOS/2_input_antimin.asc +++ b/CMOS/2_input_antimin.asc @@ -1,103 +1,103 @@ -Version 4 -SHEET 1 880 680 -WIRE -528 -208 -592 -208 -WIRE -96 -208 -448 -208 -WIRE -592 -176 -592 -208 -WIRE -96 -144 -96 -208 -WIRE -96 -144 -192 -144 -WIRE 16 -144 -96 -144 -WIRE -32 -112 -384 -112 -WIRE -192 -96 -192 -144 -WIRE 16 -96 16 -144 -WIRE 256 -96 112 -96 -WIRE 512 -96 256 -96 -WIRE 704 -96 512 -96 -WIRE -240 -80 -336 -80 -WIRE -32 -80 -32 -112 -WIRE 256 -16 256 -96 -WIRE 512 -16 512 -96 -WIRE -384 32 -384 -112 -WIRE -384 32 -448 32 -WIRE -192 96 -192 0 -WIRE -96 96 -192 96 -WIRE 16 96 16 0 -WIRE 16 96 -96 96 -WIRE 112 96 112 -96 -WIRE 112 96 16 96 -WIRE -384 144 -384 32 -WIRE 208 144 208 64 -WIRE 208 144 -384 144 -WIRE 256 160 256 80 -WIRE 368 160 256 160 -WIRE 512 160 512 80 -WIRE 512 160 368 160 -WIRE -336 192 -336 -80 -WIRE -336 192 -448 192 -WIRE 144 192 -336 192 -WIRE 464 192 464 64 -WIRE 464 192 144 192 -WIRE -96 208 -96 96 -WIRE 368 240 368 160 -WIRE -336 288 -336 192 -WIRE -144 288 -336 288 -WIRE 208 320 208 144 -WIRE 320 320 208 320 -WIRE -96 352 -96 304 -WIRE 368 368 368 336 -WIRE -384 432 -384 144 -WIRE -144 432 -384 432 -WIRE 144 448 144 192 -WIRE 320 448 144 448 -WIRE -528 512 -592 512 -WIRE -96 512 -96 448 -WIRE -96 512 -448 512 -WIRE 368 528 368 464 -WIRE -592 544 -592 512 -FLAG -592 544 0 -FLAG 368 528 0 -FLAG -592 -176 0 -FLAG -448 32 A -IOPIN -448 32 In -FLAG -448 192 B -IOPIN -448 192 In -FLAG 704 -96 Y -IOPIN 704 -96 Out -SYMBOL pmos -240 0 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos -32 0 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL nmos -144 208 R0 -SYMATTR InstName M3 -SYMATTR Value N-ENH -SYMBOL nmos -144 352 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL voltage -432 -208 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -432 512 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V4 -SYMATTR Value -1 -SYMBOL nmos 320 368 R0 -SYMATTR InstName M5 -SYMATTR Value N-DLOW -SYMBOL nmos 320 240 R0 -SYMATTR InstName M6 -SYMATTR Value N-DLOW -SYMBOL pmos 208 -16 R0 -SYMATTR InstName M7 -SYMATTR Value P-DLOW -SYMBOL pmos 464 -16 R0 -SYMATTR InstName M8 -SYMATTR Value P-DLOW -TEXT 360 -184 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -528 -208 -592 -208 +WIRE -96 -208 -448 -208 +WIRE -592 -176 -592 -208 +WIRE -96 -144 -96 -208 +WIRE -96 -144 -192 -144 +WIRE 16 -144 -96 -144 +WIRE -32 -112 -384 -112 +WIRE -192 -96 -192 -144 +WIRE 16 -96 16 -144 +WIRE 256 -96 112 -96 +WIRE 512 -96 256 -96 +WIRE 704 -96 512 -96 +WIRE -240 -80 -336 -80 +WIRE -32 -80 -32 -112 +WIRE 256 -16 256 -96 +WIRE 512 -16 512 -96 +WIRE -384 32 -384 -112 +WIRE -384 32 -448 32 +WIRE -192 96 -192 0 +WIRE -96 96 -192 96 +WIRE 16 96 16 0 +WIRE 16 96 -96 96 +WIRE 112 96 112 -96 +WIRE 112 96 16 96 +WIRE -384 144 -384 32 +WIRE 208 144 208 64 +WIRE 208 144 -384 144 +WIRE 256 160 256 80 +WIRE 368 160 256 160 +WIRE 512 160 512 80 +WIRE 512 160 368 160 +WIRE -336 192 -336 -80 +WIRE -336 192 -448 192 +WIRE 144 192 -336 192 +WIRE 464 192 464 64 +WIRE 464 192 144 192 +WIRE -96 208 -96 96 +WIRE 368 240 368 160 +WIRE -336 288 -336 192 +WIRE -144 288 -336 288 +WIRE 208 320 208 144 +WIRE 320 320 208 320 +WIRE -96 352 -96 304 +WIRE 368 368 368 336 +WIRE -384 432 -384 144 +WIRE -144 432 -384 432 +WIRE 144 448 144 192 +WIRE 320 448 144 448 +WIRE -528 512 -592 512 +WIRE -96 512 -96 448 +WIRE -96 512 -448 512 +WIRE 368 528 368 464 +WIRE -592 544 -592 512 +FLAG -592 544 0 +FLAG 368 528 0 +FLAG -592 -176 0 +FLAG -448 32 A +IOPIN -448 32 In +FLAG -448 192 B +IOPIN -448 192 In +FLAG 704 -96 Y +IOPIN 704 -96 Out +SYMBOL pmos -240 0 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos -32 0 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL nmos -144 208 R0 +SYMATTR InstName M3 +SYMATTR Value N-ENH +SYMBOL nmos -144 352 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL voltage -432 -208 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -432 512 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value -1 +SYMBOL nmos 320 368 R0 +SYMATTR InstName M5 +SYMATTR Value N-DLOW +SYMBOL nmos 320 240 R0 +SYMATTR InstName M6 +SYMATTR Value N-DLOW +SYMBOL pmos 208 -16 R0 +SYMATTR InstName M7 +SYMATTR Value P-DLOW +SYMBOL pmos 464 -16 R0 +SYMATTR InstName M8 +SYMATTR Value P-DLOW +TEXT 360 -184 Left 0 !.inc ./custom.mos diff --git a/CMOS/2_input_antimin.asy b/CMOS/2_input_antimin.asy index 1b33509..2e9850b 100644 --- a/CMOS/2_input_antimin.asy +++ b/CMOS/2_input_antimin.asy @@ -1,24 +1,24 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 56 48 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 77 Center 0 MIN -TEXT 0 52 Center 0 ANTI -SYMATTR Description 2-input ANTIMIN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 77 Center 0 MIN +TEXT 0 52 Center 0 ANTI +SYMATTR Description 2-input ANTIMIN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/2_input_max.asc b/CMOS/2_input_max.asc index 6edc382..7787925 100644 --- a/CMOS/2_input_max.asc +++ b/CMOS/2_input_max.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 80 160 64 160 -WIRE 320 176 304 176 -WIRE 80 192 64 192 -FLAG 64 160 A -IOPIN 64 160 In -FLAG 64 192 B -IOPIN 64 192 In -FLAG 320 176 Y -IOPIN 320 176 Out -SYMBOL .\\2_input_antimax 128 112 R0 -SYMATTR InstName U1 -SYMBOL .\\standard_inverter 240 128 R0 -SYMATTR InstName U2 +Version 4 +SHEET 1 880 680 +WIRE 80 160 64 160 +WIRE 320 176 304 176 +WIRE 80 192 64 192 +FLAG 64 160 A +IOPIN 64 160 In +FLAG 64 192 B +IOPIN 64 192 In +FLAG 320 176 Y +IOPIN 320 176 Out +SYMBOL .\\2_input_antimax 128 112 R0 +SYMATTR InstName U1 +SYMBOL .\\standard_inverter 240 128 R0 +SYMATTR InstName U2 diff --git a/CMOS/2_input_max.asy b/CMOS/2_input_max.asy index 5552b62..a398f78 100644 --- a/CMOS/2_input_max.asy +++ b/CMOS/2_input_max.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MAX -SYMATTR Description 2-input MAX gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MAX +SYMATTR Description 2-input MAX gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/2_input_min.asc b/CMOS/2_input_min.asc index 6f991fc..becb35c 100644 --- a/CMOS/2_input_min.asc +++ b/CMOS/2_input_min.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 80 160 64 160 -WIRE 320 176 304 176 -WIRE 80 192 64 192 -FLAG 64 160 A -IOPIN 64 160 In -FLAG 64 192 B -IOPIN 64 192 In -FLAG 320 176 Y -IOPIN 320 176 Out -SYMBOL .\\2_input_antimin 128 112 R0 -SYMATTR InstName U1 -SYMBOL .\\standard_inverter 240 128 R0 -SYMATTR InstName U2 +Version 4 +SHEET 1 880 680 +WIRE 80 160 64 160 +WIRE 320 176 304 176 +WIRE 80 192 64 192 +FLAG 64 160 A +IOPIN 64 160 In +FLAG 64 192 B +IOPIN 64 192 In +FLAG 320 176 Y +IOPIN 320 176 Out +SYMBOL .\\2_input_antimin 128 112 R0 +SYMATTR InstName U1 +SYMBOL .\\standard_inverter 240 128 R0 +SYMATTR InstName U2 diff --git a/CMOS/2_input_min.asy b/CMOS/2_input_min.asy index 0efa86d..3e5b13c 100644 --- a/CMOS/2_input_min.asy +++ b/CMOS/2_input_min.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MIN -SYMATTR Description 2-input MIN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MIN +SYMATTR Description 2-input MIN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/3_input_antimax.asc b/CMOS/3_input_antimax.asc index 4a394af..b32cc6d 100644 --- a/CMOS/3_input_antimax.asc +++ b/CMOS/3_input_antimax.asc @@ -1,135 +1,135 @@ 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+TEXT 240 -240 Left 0 !.inc ./custom.mos diff --git a/CMOS/3_input_antimin.asc b/CMOS/3_input_antimin.asc index 67da610..e920541 100644 --- a/CMOS/3_input_antimin.asc +++ b/CMOS/3_input_antimin.asc @@ -1,137 +1,137 @@ -Version 4 -SHEET 1 960 680 -WIRE -208 -288 -240 -288 -WIRE 16 -288 -128 -288 -WIRE -240 -256 -240 -288 -WIRE 16 -192 16 -288 -WIRE 16 -192 -176 -192 -WIRE 208 -192 16 -192 -WIRE 624 -176 384 -176 -WIRE 880 -176 624 -176 -WIRE -176 -160 -176 -192 -WIRE 16 -160 16 -192 -WIRE 208 -160 208 -192 -WIRE -272 -144 -384 -144 -WIRE -224 -144 -272 -144 -WIRE -32 -144 -80 -144 -WIRE 160 -144 112 -144 -WIRE 624 -112 624 -176 -WIRE -272 -32 -272 -144 -WIRE 528 -32 -272 -32 -WIRE 576 -32 528 -32 -WIRE -80 0 -80 -144 -WIRE -80 0 -384 0 -WIRE 480 0 -80 0 -WIRE 624 16 624 -16 -WIRE 112 32 112 -144 -WIRE 112 32 -128 32 -WIRE 336 32 112 32 -WIRE -176 64 -176 -64 -WIRE 16 64 16 -64 -WIRE 16 64 -176 64 -WIRE 208 64 208 -64 -WIRE 208 64 16 64 -WIRE 384 64 384 -176 -WIRE 384 64 208 64 -WIRE 16 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InstName V1 -SYMATTR Value 1 -SYMBOL voltage -112 544 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT 224 -248 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 960 680 +WIRE -208 -288 -240 -288 +WIRE 16 -288 -128 -288 +WIRE -240 -256 -240 -288 +WIRE 16 -192 16 -288 +WIRE 16 -192 -176 -192 +WIRE 208 -192 16 -192 +WIRE 624 -176 384 -176 +WIRE 880 -176 624 -176 +WIRE -176 -160 -176 -192 +WIRE 16 -160 16 -192 +WIRE 208 -160 208 -192 +WIRE -272 -144 -384 -144 +WIRE -224 -144 -272 -144 +WIRE -32 -144 -80 -144 +WIRE 160 -144 112 -144 +WIRE 624 -112 624 -176 +WIRE -272 -32 -272 -144 +WIRE 528 -32 -272 -32 +WIRE 576 -32 528 -32 +WIRE -80 0 -80 -144 +WIRE -80 0 -384 0 +WIRE 480 0 -80 0 +WIRE 624 16 624 -16 +WIRE 112 32 112 -144 +WIRE 112 32 -128 32 +WIRE 336 32 112 32 +WIRE -176 64 -176 -64 +WIRE 16 64 16 -64 +WIRE 16 64 -176 64 +WIRE 208 64 208 -64 +WIRE 208 64 16 64 +WIRE 384 64 384 -176 +WIRE 384 64 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Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -112 544 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT 224 -248 Left 0 !.inc ./custom.mos diff --git a/CMOS/buffer.asc b/CMOS/buffer.asc index 5947710..3d8de74 100644 --- a/CMOS/buffer.asc +++ b/CMOS/buffer.asc @@ -1,12 +1,12 @@ -Version 4 -SHEET 1 944 680 -WIRE 0 80 -16 80 -WIRE 240 80 224 80 -FLAG -16 80 A -IOPIN -16 80 In -FLAG 240 80 Y -IOPIN 240 80 Out -SYMBOL .\\standard_inverter 48 32 R0 -SYMATTR InstName U1 -SYMBOL .\\standard_inverter 160 32 R0 -SYMATTR InstName U2 +Version 4 +SHEET 1 944 680 +WIRE 0 80 -16 80 +WIRE 240 80 224 80 +FLAG -16 80 A +IOPIN -16 80 In +FLAG 240 80 Y +IOPIN 240 80 Out +SYMBOL .\\standard_inverter 48 32 R0 +SYMATTR InstName U1 +SYMBOL .\\standard_inverter 160 32 R0 +SYMATTR InstName U2 diff --git a/CMOS/buffer.asy b/CMOS/buffer.asy index e92d13d..a659405 100644 --- a/CMOS/buffer.asy +++ b/CMOS/buffer.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 BUF -SYMATTR Description Buffer -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 BUF +SYMATTR Description Buffer +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/clamp_down.asc b/CMOS/clamp_down.asc index a465876..2ca37a8 100644 --- a/CMOS/clamp_down.asc +++ b/CMOS/clamp_down.asc @@ -1,40 +1,40 @@ -Version 4 -SHEET 1 940 680 -WIRE 304 -128 208 -128 -WIRE 208 -112 208 -128 -WIRE 304 -64 304 -128 -WIRE 256 -48 192 -48 -WIRE -96 144 -160 144 -WIRE 192 144 192 -48 -WIRE 192 144 16 144 -WIRE 304 144 304 32 -WIRE 448 144 304 144 -WIRE 304 272 304 144 -WIRE 192 352 192 144 -WIRE 256 352 192 352 -WIRE 16 432 -32 432 -WIRE 304 432 304 368 -WIRE 304 432 96 432 -WIRE -32 464 -32 432 -FLAG -32 464 0 -FLAG 208 -112 0 -FLAG -160 144 A -IOPIN -160 144 In -FLAG 448 144 Y -IOPIN 448 144 Out -SYMBOL voltage 112 432 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -SYMBOL pmos 256 32 M180 -SYMATTR InstName M3 -SYMATTR Value P-DLOW -SYMBOL nmos 256 272 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL .\\negative_threshold_inverter -48 96 R0 -SYMATTR InstName U1 -TEXT 424 -136 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 940 680 +WIRE 304 -128 208 -128 +WIRE 208 -112 208 -128 +WIRE 304 -64 304 -128 +WIRE 256 -48 192 -48 +WIRE -96 144 -160 144 +WIRE 192 144 192 -48 +WIRE 192 144 16 144 +WIRE 304 144 304 32 +WIRE 448 144 304 144 +WIRE 304 272 304 144 +WIRE 192 352 192 144 +WIRE 256 352 192 352 +WIRE 16 432 -32 432 +WIRE 304 432 304 368 +WIRE 304 432 96 432 +WIRE -32 464 -32 432 +FLAG -32 464 0 +FLAG 208 -112 0 +FLAG -160 144 A +IOPIN -160 144 In +FLAG 448 144 Y +IOPIN 448 144 Out +SYMBOL voltage 112 432 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +SYMBOL pmos 256 32 M180 +SYMATTR InstName M3 +SYMATTR Value P-DLOW +SYMBOL nmos 256 272 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL .\\negative_threshold_inverter -48 96 R0 +SYMATTR InstName U1 +TEXT 424 -136 Left 0 !.inc ./custom.mos diff --git a/CMOS/clamp_down.asy b/CMOS/clamp_down.asy index 3fccbd7..cc88457 100644 --- a/CMOS/clamp_down.asy +++ b/CMOS/clamp_down.asy @@ -1,20 +1,20 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MIN -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP DOWN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MIN +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP DOWN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/clamp_up.asc b/CMOS/clamp_up.asc index 1205e4a..ae5ada0 100644 --- a/CMOS/clamp_up.asc +++ b/CMOS/clamp_up.asc @@ -1,38 +1,38 @@ -Version 4 -SHEET 1 924 680 -WIRE 80 -160 32 -160 -WIRE 352 -160 160 -160 -WIRE 32 -128 32 -160 -WIRE 352 -96 352 -160 -WIRE 304 -80 256 -80 -WIRE -16 96 -96 96 -WIRE 256 96 256 -80 -WIRE 256 96 96 96 -WIRE 352 96 352 0 -WIRE 480 96 352 96 -WIRE 352 240 352 96 -WIRE 256 320 256 96 -WIRE 304 320 256 320 -WIRE 352 400 352 336 -FLAG 32 -128 0 -FLAG 352 400 0 -FLAG -96 96 A -IOPIN -96 96 In -FLAG 480 96 Y -IOPIN 480 96 Out -SYMBOL voltage 176 -160 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL pmos 304 0 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL nmos 304 240 R0 -SYMATTR InstName M4 -SYMATTR Value N-DLOW -SYMBOL .\\positive_threshold_inverter 32 48 R0 -SYMATTR InstName U1 -TEXT -136 296 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 924 680 +WIRE 80 -160 32 -160 +WIRE 352 -160 160 -160 +WIRE 32 -128 32 -160 +WIRE 352 -96 352 -160 +WIRE 304 -80 256 -80 +WIRE -16 96 -96 96 +WIRE 256 96 256 -80 +WIRE 256 96 96 96 +WIRE 352 96 352 0 +WIRE 480 96 352 96 +WIRE 352 240 352 96 +WIRE 256 320 256 96 +WIRE 304 320 256 320 +WIRE 352 400 352 336 +FLAG 32 -128 0 +FLAG 352 400 0 +FLAG -96 96 A +IOPIN -96 96 In +FLAG 480 96 Y +IOPIN 480 96 Out +SYMBOL voltage 176 -160 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL pmos 304 0 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL nmos 304 240 R0 +SYMATTR InstName M4 +SYMATTR Value N-DLOW +SYMBOL .\\positive_threshold_inverter 32 48 R0 +SYMATTR InstName U1 +TEXT -136 296 Left 0 !.inc ./custom.mos diff --git a/CMOS/clamp_up.asy b/CMOS/clamp_up.asy index b4ebc93..5504d00 100644 --- a/CMOS/clamp_up.asy +++ b/CMOS/clamp_up.asy @@ -1,20 +1,20 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MAX -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP UP gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MAX +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP UP gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/consensus.asc b/CMOS/consensus.asc index 15d3dc6..9da0552 100644 --- a/CMOS/consensus.asc +++ b/CMOS/consensus.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 32 144 16 144 -WIRE 272 160 256 160 -WIRE 32 176 16 176 -FLAG 16 144 A -IOPIN 16 144 In -FLAG 16 176 B -IOPIN 16 176 In -FLAG 272 160 Y -IOPIN 272 160 Out -SYMBOL .\\inverting_consensus 80 96 R0 -SYMATTR InstName U1 -SYMBOL .\\standard_inverter 192 112 R0 -SYMATTR InstName U2 +Version 4 +SHEET 1 880 680 +WIRE 32 144 16 144 +WIRE 272 160 256 160 +WIRE 32 176 16 176 +FLAG 16 144 A +IOPIN 16 144 In +FLAG 16 176 B +IOPIN 16 176 In +FLAG 272 160 Y +IOPIN 272 160 Out +SYMBOL .\\inverting_consensus 80 96 R0 +SYMATTR InstName U1 +SYMBOL .\\standard_inverter 192 112 R0 +SYMATTR InstName U2 diff --git a/CMOS/consensus.asy b/CMOS/consensus.asy index 1201fa4..b7aff7d 100644 --- a/CMOS/consensus.asy +++ b/CMOS/consensus.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 CON -SYMATTR Description 2-input consensus gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 CON +SYMATTR Description 2-input consensus gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/custom.mos b/CMOS/custom.mos index 9f38457..d63d327 100644 --- a/CMOS/custom.mos +++ b/CMOS/custom.mos @@ -1,24 +1,24 @@ -.model P-DEP VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - -.model N-DEP VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) - - - -.model P-DLOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - -.model N-DLOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) - - - - - - -.model P-ENH VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - -.model N-ENH VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) - - - -.model P-ELOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - +.model P-DEP VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + +.model N-DEP VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) + + + +.model P-DLOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + +.model N-DLOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) + + + + + + +.model P-ENH VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + +.model N-ENH VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) + + + +.model P-ELOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + .model N-ELOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) \ No newline at end of file diff --git a/CMOS/decrement.asc b/CMOS/decrement.asc index e38789b..9ed740e 100644 --- a/CMOS/decrement.asc +++ b/CMOS/decrement.asc @@ -1,73 +1,73 @@ -Version 4 -SHEET 1 880 680 -WIRE -336 -192 -400 -192 -WIRE 144 -192 -256 -192 -WIRE -400 -160 -400 -192 -WIRE 144 -144 144 -192 -WIRE 96 -128 16 -128 -WIRE 144 -16 144 -48 -WIRE 672 -16 144 -16 -WIRE 768 -16 672 -16 -WIRE 144 32 144 -16 -WIRE 16 48 16 -128 -WIRE 16 48 -256 48 -WIRE 16 112 16 48 -WIRE 96 112 16 112 -WIRE 144 160 144 128 -WIRE 672 208 672 -16 -WIRE 480 240 192 240 -WIRE 144 288 144 256 -WIRE 624 288 560 288 -WIRE 16 352 16 112 -WIRE 272 352 16 352 -WIRE 560 352 560 288 -WIRE 560 352 272 352 -WIRE 672 368 672 304 -WIRE 272 448 272 352 -WIRE 320 448 272 448 -WIRE 480 448 480 240 -WIRE 480 448 432 448 -WIRE 624 448 480 448 -WIRE -336 512 -400 512 -WIRE 672 512 672 464 -WIRE 672 512 -256 512 -WIRE -400 544 -400 512 -FLAG -400 -160 0 -FLAG 144 288 0 -FLAG -400 544 0 -FLAG -256 48 A -IOPIN -256 48 In -FLAG 768 -16 Y -IOPIN 768 -16 Out -SYMBOL nmos 96 32 R0 -SYMATTR InstName M1 -SYMATTR Value N-ELOW -SYMBOL pmos 192 160 M0 -SYMATTR InstName M2 -SYMATTR Value P-DLOW -SYMBOL pmos 96 -48 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL voltage -240 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -240 512 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -SYMBOL nmos 624 208 R0 -SYMATTR InstName M6 -SYMATTR Value N-ELOW -SYMBOL nmos 624 368 R0 -SYMATTR InstName M7 -SYMATTR Value N-ENH -SYMBOL .\\positive_threshold_inverter 368 400 R0 -SYMATTR InstName U1 -TEXT 536 -184 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -336 -192 -400 -192 +WIRE 144 -192 -256 -192 +WIRE -400 -160 -400 -192 +WIRE 144 -144 144 -192 +WIRE 96 -128 16 -128 +WIRE 144 -16 144 -48 +WIRE 672 -16 144 -16 +WIRE 768 -16 672 -16 +WIRE 144 32 144 -16 +WIRE 16 48 16 -128 +WIRE 16 48 -256 48 +WIRE 16 112 16 48 +WIRE 96 112 16 112 +WIRE 144 160 144 128 +WIRE 672 208 672 -16 +WIRE 480 240 192 240 +WIRE 144 288 144 256 +WIRE 624 288 560 288 +WIRE 16 352 16 112 +WIRE 272 352 16 352 +WIRE 560 352 560 288 +WIRE 560 352 272 352 +WIRE 672 368 672 304 +WIRE 272 448 272 352 +WIRE 320 448 272 448 +WIRE 480 448 480 240 +WIRE 480 448 432 448 +WIRE 624 448 480 448 +WIRE -336 512 -400 512 +WIRE 672 512 672 464 +WIRE 672 512 -256 512 +WIRE -400 544 -400 512 +FLAG -400 -160 0 +FLAG 144 288 0 +FLAG -400 544 0 +FLAG -256 48 A +IOPIN -256 48 In +FLAG 768 -16 Y +IOPIN 768 -16 Out +SYMBOL nmos 96 32 R0 +SYMATTR InstName M1 +SYMATTR Value N-ELOW +SYMBOL pmos 192 160 M0 +SYMATTR InstName M2 +SYMATTR Value P-DLOW +SYMBOL pmos 96 -48 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL voltage -240 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -240 512 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +SYMBOL nmos 624 208 R0 +SYMATTR InstName M6 +SYMATTR Value N-ELOW +SYMBOL nmos 624 368 R0 +SYMATTR InstName M7 +SYMATTR Value N-ENH +SYMBOL .\\positive_threshold_inverter 368 400 R0 +SYMATTR InstName U1 +TEXT 536 -184 Left 0 !.inc ./custom.mos diff --git a/CMOS/decrement.asy b/CMOS/decrement.asy index 3e3d8f7..4d5540b 100644 --- a/CMOS/decrement.asy +++ b/CMOS/decrement.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 -1 -SYMATTR Description Decrement gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 -1 +SYMATTR Description Decrement gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/equality.asc b/CMOS/equality.asc index 58bc12c..4cfc348 100644 --- a/CMOS/equality.asc +++ b/CMOS/equality.asc @@ -1,169 +1,169 @@ -Version 4 -SHEET 1 944 868 -WIRE -400 -240 -448 -240 -WIRE -128 -240 -320 -240 -WIRE 128 -240 -128 -240 -WIRE 704 -240 128 -240 -WIRE -448 -208 -448 -240 -WIRE 448 -176 224 -176 -WIRE -128 -128 -128 -240 -WIRE 128 -128 128 -240 -WIRE 448 -128 448 -176 -WIRE 704 -128 704 -240 -WIRE -224 -112 -592 -112 -WIRE -176 -112 -224 -112 -WIRE 80 -112 32 -112 -WIRE 400 -112 288 -112 -WIRE 656 -112 560 -112 -WIRE -224 -16 -224 -112 -WIRE 32 -16 32 -112 -WIRE 32 -16 -224 -16 -WIRE -592 48 -592 -112 -WIRE -592 48 -784 48 -WIRE -544 48 -592 48 -WIRE 288 48 288 -112 -WIRE 288 48 -432 48 -WIRE 560 48 560 -112 -WIRE 560 48 288 48 -WIRE -128 64 -128 -32 -WIRE 128 64 128 -32 -WIRE 448 64 448 -32 -WIRE 704 64 704 -32 -WIRE -176 80 -288 80 -WIRE 80 80 -32 80 -WIRE 400 80 352 80 -WIRE 656 80 608 80 -WIRE 352 176 352 80 -WIRE 352 176 -384 176 -WIRE 608 176 608 80 -WIRE 608 176 352 176 -WIRE 128 208 128 160 -WIRE 224 208 224 -176 -WIRE 224 208 128 208 -WIRE -128 272 -128 160 -WIRE 128 272 -128 272 -WIRE 448 272 448 160 -WIRE 448 272 128 272 -WIRE 704 272 704 160 -WIRE 704 272 448 272 -WIRE 864 272 704 272 -WIRE -592 352 -784 352 -WIRE -544 352 -592 352 -WIRE -384 352 -384 176 -WIRE -384 352 -432 352 -WIRE -128 384 -128 272 -WIRE 128 384 128 272 -WIRE 448 384 448 272 -WIRE 704 384 704 272 -WIRE -224 464 -224 -16 -WIRE -176 464 -224 464 -WIRE 32 464 32 -16 -WIRE 80 464 32 464 -WIRE 288 464 288 48 -WIRE 400 464 288 464 -WIRE 560 464 560 48 -WIRE 656 464 560 464 -WIRE -592 512 -592 352 -WIRE -288 512 -288 80 -WIRE -288 512 -592 512 -WIRE -32 512 -32 80 -WIRE -32 512 -288 512 -WIRE 352 512 -32 512 -WIRE 608 512 352 512 -WIRE -384 560 -384 352 -WIRE 32 560 -384 560 -WIRE -128 576 -128 480 -WIRE 128 576 128 480 -WIRE 448 576 448 480 -WIRE 704 576 704 480 -WIRE -384 656 -384 560 -WIRE -176 656 -384 656 -WIRE 32 656 32 560 -WIRE 80 656 32 656 -WIRE 352 656 352 512 -WIRE 400 656 352 656 -WIRE 608 656 608 512 -WIRE 656 656 608 656 -WIRE -400 784 -448 784 -WIRE -128 784 -128 672 -WIRE -128 784 -320 784 -WIRE 128 784 128 672 -WIRE 128 784 -128 784 -WIRE 448 784 448 672 -WIRE 448 784 128 784 -WIRE 704 784 704 672 -WIRE 704 784 448 784 -WIRE -448 816 -448 784 -FLAG -448 816 0 -FLAG -448 -208 0 -FLAG -784 48 A -IOPIN -784 48 In -FLAG -784 352 B -IOPIN -784 352 In -FLAG 864 272 Y -IOPIN 864 272 Out -SYMBOL pmos -176 -32 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos -176 160 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL pmos 80 -32 M180 -SYMATTR InstName M3 -SYMATTR Value P-ELOW -SYMBOL pmos 80 160 M180 -SYMATTR InstName M4 -SYMATTR Value P-ELOW -SYMBOL pmos 400 -32 M180 -SYMATTR InstName M5 -SYMATTR Value P-ELOW -SYMBOL pmos 400 160 M180 -SYMATTR InstName M6 -SYMATTR Value P-ELOW -SYMBOL pmos 656 -32 M180 -SYMATTR InstName M7 -SYMATTR Value P-ENH -SYMBOL pmos 656 160 M180 -SYMATTR InstName M8 -SYMATTR Value P-ENH -SYMBOL voltage -304 -240 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL nmos -176 384 R0 -SYMATTR InstName M9 -SYMATTR Value N-ENH -SYMBOL nmos -176 576 R0 -SYMATTR InstName M10 -SYMATTR Value N-ELOW -SYMBOL nmos 80 384 R0 -SYMATTR InstName M11 -SYMATTR Value N-ELOW -SYMBOL nmos 80 576 R0 -SYMATTR InstName M12 -SYMATTR Value N-ENH -SYMBOL nmos 400 384 R0 -SYMATTR InstName M13 -SYMATTR Value N-ENH -SYMBOL nmos 400 576 R0 -SYMATTR InstName M14 -SYMATTR Value N-ELOW -SYMBOL nmos 656 384 R0 -SYMATTR InstName M15 -SYMATTR Value N-ELOW -SYMBOL nmos 656 576 R0 -SYMATTR InstName M16 -SYMATTR Value N-ENH -SYMBOL voltage -304 784 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -SYMBOL .\\standard_inverter -496 0 R0 -SYMATTR InstName U1 -SYMBOL .\\standard_inverter -496 304 R0 -SYMATTR InstName U2 -TEXT -752 624 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 944 868 +WIRE -400 -240 -448 -240 +WIRE -128 -240 -320 -240 +WIRE 128 -240 -128 -240 +WIRE 704 -240 128 -240 +WIRE -448 -208 -448 -240 +WIRE 448 -176 224 -176 +WIRE -128 -128 -128 -240 +WIRE 128 -128 128 -240 +WIRE 448 -128 448 -176 +WIRE 704 -128 704 -240 +WIRE -224 -112 -592 -112 +WIRE -176 -112 -224 -112 +WIRE 80 -112 32 -112 +WIRE 400 -112 288 -112 +WIRE 656 -112 560 -112 +WIRE -224 -16 -224 -112 +WIRE 32 -16 32 -112 +WIRE 32 -16 -224 -16 +WIRE -592 48 -592 -112 +WIRE -592 48 -784 48 +WIRE -544 48 -592 48 +WIRE 288 48 288 -112 +WIRE 288 48 -432 48 +WIRE 560 48 560 -112 +WIRE 560 48 288 48 +WIRE -128 64 -128 -32 +WIRE 128 64 128 -32 +WIRE 448 64 448 -32 +WIRE 704 64 704 -32 +WIRE -176 80 -288 80 +WIRE 80 80 -32 80 +WIRE 400 80 352 80 +WIRE 656 80 608 80 +WIRE 352 176 352 80 +WIRE 352 176 -384 176 +WIRE 608 176 608 80 +WIRE 608 176 352 176 +WIRE 128 208 128 160 +WIRE 224 208 224 -176 +WIRE 224 208 128 208 +WIRE -128 272 -128 160 +WIRE 128 272 -128 272 +WIRE 448 272 448 160 +WIRE 448 272 128 272 +WIRE 704 272 704 160 +WIRE 704 272 448 272 +WIRE 864 272 704 272 +WIRE -592 352 -784 352 +WIRE -544 352 -592 352 +WIRE -384 352 -384 176 +WIRE -384 352 -432 352 +WIRE -128 384 -128 272 +WIRE 128 384 128 272 +WIRE 448 384 448 272 +WIRE 704 384 704 272 +WIRE -224 464 -224 -16 +WIRE -176 464 -224 464 +WIRE 32 464 32 -16 +WIRE 80 464 32 464 +WIRE 288 464 288 48 +WIRE 400 464 288 464 +WIRE 560 464 560 48 +WIRE 656 464 560 464 +WIRE -592 512 -592 352 +WIRE -288 512 -288 80 +WIRE -288 512 -592 512 +WIRE -32 512 -32 80 +WIRE -32 512 -288 512 +WIRE 352 512 -32 512 +WIRE 608 512 352 512 +WIRE -384 560 -384 352 +WIRE 32 560 -384 560 +WIRE -128 576 -128 480 +WIRE 128 576 128 480 +WIRE 448 576 448 480 +WIRE 704 576 704 480 +WIRE -384 656 -384 560 +WIRE -176 656 -384 656 +WIRE 32 656 32 560 +WIRE 80 656 32 656 +WIRE 352 656 352 512 +WIRE 400 656 352 656 +WIRE 608 656 608 512 +WIRE 656 656 608 656 +WIRE -400 784 -448 784 +WIRE -128 784 -128 672 +WIRE -128 784 -320 784 +WIRE 128 784 128 672 +WIRE 128 784 -128 784 +WIRE 448 784 448 672 +WIRE 448 784 128 784 +WIRE 704 784 704 672 +WIRE 704 784 448 784 +WIRE -448 816 -448 784 +FLAG -448 816 0 +FLAG -448 -208 0 +FLAG -784 48 A +IOPIN -784 48 In +FLAG -784 352 B +IOPIN -784 352 In +FLAG 864 272 Y +IOPIN 864 272 Out +SYMBOL pmos -176 -32 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos -176 160 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL pmos 80 -32 M180 +SYMATTR InstName M3 +SYMATTR Value P-ELOW +SYMBOL pmos 80 160 M180 +SYMATTR InstName M4 +SYMATTR Value P-ELOW +SYMBOL pmos 400 -32 M180 +SYMATTR InstName M5 +SYMATTR Value P-ELOW +SYMBOL pmos 400 160 M180 +SYMATTR InstName M6 +SYMATTR Value P-ELOW +SYMBOL pmos 656 -32 M180 +SYMATTR InstName M7 +SYMATTR Value P-ENH +SYMBOL pmos 656 160 M180 +SYMATTR InstName M8 +SYMATTR Value P-ENH +SYMBOL voltage -304 -240 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL nmos -176 384 R0 +SYMATTR InstName M9 +SYMATTR Value N-ENH +SYMBOL nmos -176 576 R0 +SYMATTR InstName M10 +SYMATTR Value N-ELOW +SYMBOL nmos 80 384 R0 +SYMATTR InstName M11 +SYMATTR Value N-ELOW +SYMBOL nmos 80 576 R0 +SYMATTR InstName M12 +SYMATTR Value N-ENH +SYMBOL nmos 400 384 R0 +SYMATTR InstName M13 +SYMATTR Value N-ENH +SYMBOL nmos 400 576 R0 +SYMATTR InstName M14 +SYMATTR Value N-ELOW +SYMBOL nmos 656 384 R0 +SYMATTR InstName M15 +SYMATTR Value N-ELOW +SYMBOL nmos 656 576 R0 +SYMATTR InstName M16 +SYMATTR Value N-ENH +SYMBOL voltage -304 784 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +SYMBOL .\\standard_inverter -496 0 R0 +SYMATTR InstName U1 +SYMBOL .\\standard_inverter -496 304 R0 +SYMATTR InstName U2 +TEXT -752 624 Left 0 !.inc ./custom.mos diff --git a/CMOS/equality.asy b/CMOS/equality.asy index c6470ce..14fb10a 100644 --- a/CMOS/equality.asy +++ b/CMOS/equality.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 = -SYMATTR Description 2-input equality gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 = +SYMATTR Description 2-input equality gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/gullible.asc b/CMOS/gullible.asc index ab6240d..dccd112 100644 --- a/CMOS/gullible.asc +++ b/CMOS/gullible.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 0 144 -16 144 -WIRE 240 160 224 160 -WIRE 0 176 -16 176 -FLAG -16 144 A -IOPIN -16 144 In -FLAG -16 176 B -IOPIN -16 176 In -FLAG 240 160 Y -IOPIN 240 160 Out -SYMBOL .\\inverting_gullible 48 96 R0 -SYMATTR InstName U1 -SYMBOL .\\standard_inverter 160 112 R0 -SYMATTR InstName U2 +Version 4 +SHEET 1 880 680 +WIRE 0 144 -16 144 +WIRE 240 160 224 160 +WIRE 0 176 -16 176 +FLAG -16 144 A +IOPIN -16 144 In +FLAG -16 176 B +IOPIN -16 176 In +FLAG 240 160 Y +IOPIN 240 160 Out +SYMBOL .\\inverting_gullible 48 96 R0 +SYMATTR InstName U1 +SYMBOL .\\standard_inverter 160 112 R0 +SYMATTR InstName U2 diff --git a/CMOS/gullible.asy b/CMOS/gullible.asy index cd75b7e..7d8ba23 100644 --- a/CMOS/gullible.asy +++ b/CMOS/gullible.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 GUL -SYMATTR Description 2-input gullible gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 GUL +SYMATTR Description 2-input gullible gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/increment.asc b/CMOS/increment.asc index 533c432..7a09449 100644 --- a/CMOS/increment.asc +++ b/CMOS/increment.asc @@ -1,73 +1,73 @@ -Version 4 -SHEET 1 880 680 -WIRE -416 -192 -480 -192 -WIRE 416 -192 -336 -192 -WIRE -480 -160 -480 -192 -WIRE 416 -112 416 -192 -WIRE 64 -96 -240 -96 -WIRE 128 -96 64 -96 -WIRE 304 -96 240 -96 -WIRE 368 -96 304 -96 -WIRE -64 -64 -160 -64 -WIRE -160 -32 -160 -64 -WIRE -64 0 -64 -64 -WIRE 304 16 304 -96 -WIRE 304 16 -16 16 -WIRE 416 64 416 -16 -WIRE 64 80 64 -96 -WIRE 368 80 64 80 -WIRE -64 144 -64 96 -WIRE -240 160 -240 -96 -WIRE -240 160 -336 160 -WIRE -160 160 -240 160 -WIRE -112 160 -160 160 -WIRE -64 304 -64 240 -WIRE 416 304 416 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48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 +1 -SYMATTR Description Increment gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 +1 +SYMATTR Description Increment gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/inverting_consensus.asc b/CMOS/inverting_consensus.asc index ef326e8..01357f4 100644 --- a/CMOS/inverting_consensus.asc +++ b/CMOS/inverting_consensus.asc @@ -1,100 +1,100 @@ -Version 4 -SHEET 1 880 680 -WIRE -368 -224 -448 -224 -WIRE -16 -224 -288 -224 -WIRE -448 -192 -448 -224 -WIRE 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-PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 CON +SYMATTR Description 2-input inverting consensus +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/inverting_gullible.asc b/CMOS/inverting_gullible.asc index 8a4888c..26a542e 100644 --- a/CMOS/inverting_gullible.asc +++ b/CMOS/inverting_gullible.asc @@ -1,162 +1,162 @@ -Version 4 -SHEET 1 1168 708 -WIRE -352 -208 -384 -208 -WIRE -80 -208 -272 -208 -WIRE 176 -208 -80 -208 -WIRE -384 -176 -384 -208 -WIRE 464 -160 288 -160 -WIRE 720 -160 464 -160 -WIRE 976 -160 720 -160 -WIRE 1088 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+SYMATTR InstName M8 +SYMATTR Value N-ELOW +SYMBOL voltage -256 -208 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -256 624 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +SYMBOL nmos 416 -80 R0 +SYMATTR InstName M9 +SYMATTR Value N-DLOW +SYMBOL nmos 672 -80 R0 +SYMATTR InstName M10 +SYMATTR Value N-ELOW +SYMBOL nmos 928 -80 R0 +SYMATTR InstName M11 +SYMATTR Value N-ELOW +SYMBOL pmos 416 112 R0 +SYMATTR InstName M12 +SYMATTR Value P-DLOW +SYMBOL pmos 672 112 R0 +SYMATTR InstName M13 +SYMATTR Value P-ELOW +SYMBOL pmos 928 112 R0 +SYMATTR InstName M14 +SYMATTR Value P-ELOW +SYMBOL nmos 416 304 R0 +SYMATTR InstName M15 +SYMATTR Value N-DLOW +SYMBOL pmos 416 496 R0 +SYMATTR InstName M16 +SYMATTR Value P-DLOW +TEXT 280 -272 Left 0 !.inc ./custom.mos diff --git a/CMOS/inverting_gullible.asy b/CMOS/inverting_gullible.asy index 3e6991f..34a9c84 100644 --- a/CMOS/inverting_gullible.asy +++ b/CMOS/inverting_gullible.asy @@ -1,23 +1,23 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 56 48 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 GUL -SYMATTR Description 2-input inverting gullible -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 GUL +SYMATTR Description 2-input inverting gullible +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/CMOS/is_false.asc b/CMOS/is_false.asc index 44db15a..c02d271 100644 --- a/CMOS/is_false.asc +++ b/CMOS/is_false.asc @@ -1,10 +1,10 @@ -Version 4 -SHEET 1 924 680 -WIRE -112 128 -128 128 -WIRE 16 128 0 128 -FLAG -128 128 A -IOPIN -128 128 In -FLAG 16 128 Y -IOPIN 16 128 Out -SYMBOL .\\negative_threshold_inverter -64 80 R0 -SYMATTR InstName U1 +Version 4 +SHEET 1 924 680 +WIRE -112 128 -128 128 +WIRE 16 128 0 128 +FLAG -128 128 A +IOPIN -128 128 In +FLAG 16 128 Y +IOPIN 16 128 Out +SYMBOL .\\negative_threshold_inverter -64 80 R0 +SYMATTR InstName U1 diff --git a/CMOS/is_false.asy b/CMOS/is_false.asy index e5e3fee..2204505 100644 --- a/CMOS/is_false.asy +++ b/CMOS/is_false.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 =- -SYMATTR Description IS FALSE gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =- +SYMATTR Description IS FALSE gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/is_true.asc b/CMOS/is_true.asc index 37700f7..199c42a 100644 --- a/CMOS/is_true.asc +++ b/CMOS/is_true.asc @@ -1,12 +1,12 @@ -Version 4 -SHEET 1 924 680 -WIRE -16 96 -32 96 -WIRE 224 96 208 96 -FLAG -32 96 A -IOPIN -32 96 In -FLAG 224 96 Y -IOPIN 224 96 Out -SYMBOL .\\positive_threshold_inverter 32 48 R0 -SYMATTR InstName U1 -SYMBOL .\\negative_threshold_inverter 144 48 R0 -SYMATTR InstName U2 +Version 4 +SHEET 1 924 680 +WIRE -16 96 -32 96 +WIRE 224 96 208 96 +FLAG -32 96 A +IOPIN -32 96 In +FLAG 224 96 Y +IOPIN 224 96 Out +SYMBOL .\\positive_threshold_inverter 32 48 R0 +SYMATTR InstName U1 +SYMBOL .\\negative_threshold_inverter 144 48 R0 +SYMATTR InstName U2 diff --git a/CMOS/is_true.asy b/CMOS/is_true.asy index 5105d90..0edb8b6 100644 --- a/CMOS/is_true.asy +++ b/CMOS/is_true.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 =+ -SYMATTR Description IS TRUE gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =+ +SYMATTR Description IS TRUE gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/is_unknown.asc b/CMOS/is_unknown.asc index efe88fe..4789591 100644 --- a/CMOS/is_unknown.asc +++ b/CMOS/is_unknown.asc @@ -1,67 +1,67 @@ -Version 4 -SHEET 1 956 680 -WIRE -288 -192 -336 -192 -WIRE 304 -192 -208 -192 -WIRE -336 -160 -336 -192 -WIRE 304 -160 304 -192 -WIRE 256 -144 112 -144 -WIRE 304 -32 304 -64 -WIRE 256 -16 192 -16 -WIRE -112 96 -208 96 -WIRE -48 96 -112 96 -WIRE 192 96 192 -16 -WIRE 192 96 64 96 -WIRE 304 96 304 64 -WIRE 544 96 304 96 -WIRE 656 96 544 96 -WIRE -112 176 -112 96 -WIRE 112 176 112 -144 -WIRE 112 176 -112 176 -WIRE 432 176 112 176 -WIRE 304 240 304 96 -WIRE 544 240 544 96 -WIRE 192 320 192 96 -WIRE 256 320 192 320 -WIRE 432 320 432 176 -WIRE 496 320 432 320 -WIRE -288 400 -336 400 -WIRE 304 400 304 336 -WIRE 304 400 -208 400 -WIRE 544 400 544 336 -WIRE 544 400 304 400 -WIRE -336 432 -336 400 -FLAG -336 -160 0 -FLAG -336 432 0 -FLAG -208 96 A -IOPIN -208 96 In -FLAG 656 96 Y -IOPIN 656 96 Out -SYMBOL voltage -192 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -192 400 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -SYMBOL nmos 256 240 R0 -SYMATTR InstName M3 -SYMATTR Value N-ELOW -SYMBOL nmos 496 240 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL pmos 256 64 M180 -SYMATTR InstName M5 -SYMATTR Value P-ENH -SYMBOL pmos 256 -64 M180 -SYMATTR InstName M6 -SYMATTR Value P-ELOW -SYMBOL .\\negative_threshold_inverter 0 48 R0 -SYMATTR InstName U1 -TEXT 360 -208 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 956 680 +WIRE -288 -192 -336 -192 +WIRE 304 -192 -208 -192 +WIRE -336 -160 -336 -192 +WIRE 304 -160 304 -192 +WIRE 256 -144 112 -144 +WIRE 304 -32 304 -64 +WIRE 256 -16 192 -16 +WIRE -112 96 -208 96 +WIRE -48 96 -112 96 +WIRE 192 96 192 -16 +WIRE 192 96 64 96 +WIRE 304 96 304 64 +WIRE 544 96 304 96 +WIRE 656 96 544 96 +WIRE -112 176 -112 96 +WIRE 112 176 112 -144 +WIRE 112 176 -112 176 +WIRE 432 176 112 176 +WIRE 304 240 304 96 +WIRE 544 240 544 96 +WIRE 192 320 192 96 +WIRE 256 320 192 320 +WIRE 432 320 432 176 +WIRE 496 320 432 320 +WIRE -288 400 -336 400 +WIRE 304 400 304 336 +WIRE 304 400 -208 400 +WIRE 544 400 544 336 +WIRE 544 400 304 400 +WIRE -336 432 -336 400 +FLAG -336 -160 0 +FLAG -336 432 0 +FLAG -208 96 A +IOPIN -208 96 In +FLAG 656 96 Y +IOPIN 656 96 Out +SYMBOL voltage -192 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -192 400 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +SYMBOL nmos 256 240 R0 +SYMATTR InstName M3 +SYMATTR Value N-ELOW +SYMBOL nmos 496 240 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL pmos 256 64 M180 +SYMATTR InstName M5 +SYMATTR Value P-ENH +SYMBOL pmos 256 -64 M180 +SYMATTR InstName M6 +SYMATTR Value P-ELOW +SYMBOL .\\negative_threshold_inverter 0 48 R0 +SYMATTR InstName U1 +TEXT 360 -208 Left 0 !.inc ./custom.mos diff --git a/CMOS/is_unknown.asy b/CMOS/is_unknown.asy index 8ffb820..49da4de 100644 --- a/CMOS/is_unknown.asy +++ b/CMOS/is_unknown.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 =0 -SYMATTR Description IS UNKNOWN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =0 +SYMATTR Description IS UNKNOWN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/monadic_decoder.asc b/CMOS/monadic_decoder.asc index 5791a49..7b5079e 100644 --- a/CMOS/monadic_decoder.asc +++ b/CMOS/monadic_decoder.asc @@ -1,80 +1,80 @@ -Version 4 -SHEET 1 880 680 -WIRE -48 -144 -112 -144 -WIRE 224 -144 64 -144 -WIRE 288 -144 224 -144 -WIRE 64 -64 32 -64 -WIRE 336 -64 144 -64 -WIRE 32 -32 32 -64 -WIRE 336 -32 336 -64 -WIRE 288 -16 160 -16 -WIRE -112 32 -112 -144 -WIRE -112 32 -224 32 -WIRE 336 80 336 64 -WIRE 224 96 224 -144 -WIRE 288 96 224 96 -WIRE 336 208 336 176 -WIRE 576 208 336 208 -WIRE 720 208 576 208 -WIRE -112 240 -112 32 -WIRE 160 240 160 -16 -WIRE 160 240 -112 240 -WIRE 464 240 160 240 -WIRE 336 272 336 208 -WIRE 576 272 576 208 -WIRE 224 352 224 96 -WIRE 288 352 224 352 -WIRE 464 352 464 240 -WIRE 528 352 464 352 -WIRE 64 400 32 400 -WIRE 336 400 336 368 -WIRE 336 400 144 400 -WIRE 576 400 576 368 -WIRE 576 400 336 400 -WIRE 32 432 32 400 -WIRE -112 496 -112 240 -WIRE -48 496 -112 496 -WIRE 288 496 176 496 -FLAG -224 32 A -IOPIN -224 32 In -FLAG 288 -144 Y1 -IOPIN 288 -144 Out -FLAG 288 496 Y3 -IOPIN 288 496 Out -FLAG 32 -32 0 -FLAG 32 432 0 -FLAG 720 208 Y2 -IOPIN 720 208 Out -SYMBOL .\\negative_threshold_inverter 0 -192 R0 -SYMATTR InstName U1 -SYMBOL .\\positive_threshold_inverter 0 448 R0 -SYMATTR InstName U2 -SYMBOL .\\negative_threshold_inverter 112 448 R0 -SYMATTR InstName U3 -SYMBOL voltage 160 -64 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage 160 400 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -SYMBOL pmos 288 64 M180 -SYMATTR InstName M1 -SYMATTR Value P-ELOW -SYMBOL pmos 288 176 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL nmos 288 272 R0 -SYMATTR InstName M3 -SYMATTR Value N-ELOW -SYMBOL nmos 528 272 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -TEXT 496 -120 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -48 -144 -112 -144 +WIRE 224 -144 64 -144 +WIRE 288 -144 224 -144 +WIRE 64 -64 32 -64 +WIRE 336 -64 144 -64 +WIRE 32 -32 32 -64 +WIRE 336 -32 336 -64 +WIRE 288 -16 160 -16 +WIRE -112 32 -112 -144 +WIRE -112 32 -224 32 +WIRE 336 80 336 64 +WIRE 224 96 224 -144 +WIRE 288 96 224 96 +WIRE 336 208 336 176 +WIRE 576 208 336 208 +WIRE 720 208 576 208 +WIRE -112 240 -112 32 +WIRE 160 240 160 -16 +WIRE 160 240 -112 240 +WIRE 464 240 160 240 +WIRE 336 272 336 208 +WIRE 576 272 576 208 +WIRE 224 352 224 96 +WIRE 288 352 224 352 +WIRE 464 352 464 240 +WIRE 528 352 464 352 +WIRE 64 400 32 400 +WIRE 336 400 336 368 +WIRE 336 400 144 400 +WIRE 576 400 576 368 +WIRE 576 400 336 400 +WIRE 32 432 32 400 +WIRE -112 496 -112 240 +WIRE -48 496 -112 496 +WIRE 288 496 176 496 +FLAG -224 32 A +IOPIN -224 32 In +FLAG 288 -144 Y1 +IOPIN 288 -144 Out +FLAG 288 496 Y3 +IOPIN 288 496 Out +FLAG 32 -32 0 +FLAG 32 432 0 +FLAG 720 208 Y2 +IOPIN 720 208 Out +SYMBOL .\\negative_threshold_inverter 0 -192 R0 +SYMATTR InstName U1 +SYMBOL .\\positive_threshold_inverter 0 448 R0 +SYMATTR InstName U2 +SYMBOL .\\negative_threshold_inverter 112 448 R0 +SYMATTR InstName U3 +SYMBOL voltage 160 -64 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage 160 400 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +SYMBOL pmos 288 64 M180 +SYMATTR InstName M1 +SYMATTR Value P-ELOW +SYMBOL pmos 288 176 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL nmos 288 272 R0 +SYMATTR InstName M3 +SYMATTR Value N-ELOW +SYMBOL nmos 528 272 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +TEXT 496 -120 Left 0 !.inc ./custom.mos diff --git a/CMOS/monadic_decoder.asy b/CMOS/monadic_decoder.asy index 7e2d830..e4f8037 100644 --- a/CMOS/monadic_decoder.asy +++ b/CMOS/monadic_decoder.asy @@ -1,28 +1,28 @@ -Version 4 -SymbolType CELL -LINE Normal 64 80 32 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 128 32 32 -LINE Normal -32 128 32 128 -LINE Normal -32 32 -32 128 -LINE Normal 64 48 32 48 -LINE Normal 64 112 32 112 -LINE Normal -64 80 -32 80 -TEXT -20 80 Left 0 = -TEXT 3 46 Left 0 - -TEXT 9 46 Left 0 - -TEXT 10 80 Center 0 0 -TEXT 10 112 Center 0 + -SYMATTR Description Monadic decoder gate -PIN -64 80 NONE 8 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 8 -PINATTR PinName Y1 -PINATTR SpiceOrder 2 -PIN 64 80 NONE 8 -PINATTR PinName Y2 -PINATTR SpiceOrder 3 -PIN 64 112 NONE 8 -PINATTR PinName Y3 -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 64 80 32 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 128 32 32 +LINE Normal -32 128 32 128 +LINE Normal -32 32 -32 128 +LINE Normal 64 48 32 48 +LINE Normal 64 112 32 112 +LINE Normal -64 80 -32 80 +TEXT -20 80 Left 0 = +TEXT 3 46 Left 0 - +TEXT 9 46 Left 0 - +TEXT 10 80 Center 0 0 +TEXT 10 112 Center 0 + +SYMATTR Description Monadic decoder gate +PIN -64 80 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 8 +PINATTR PinName Y1 +PINATTR SpiceOrder 2 +PIN 64 80 NONE 8 +PINATTR PinName Y2 +PINATTR SpiceOrder 3 +PIN 64 112 NONE 8 +PINATTR PinName Y3 +PINATTR SpiceOrder 4 diff --git a/CMOS/negative_threshold_inverter.asc b/CMOS/negative_threshold_inverter.asc index 7380e83..981d829 100644 --- a/CMOS/negative_threshold_inverter.asc +++ b/CMOS/negative_threshold_inverter.asc @@ -1,45 +1,45 @@ -Version 4 -SHEET 1 924 680 -WIRE -288 -160 -336 -160 -WIRE 96 -160 -208 -160 -WIRE -336 -128 -336 -160 -WIRE 96 -96 96 -160 -WIRE 48 -80 0 -80 -WIRE 0 96 0 -80 -WIRE 0 96 -208 96 -WIRE 96 96 96 0 -WIRE 256 96 96 96 -WIRE 96 240 96 96 -WIRE 0 320 0 96 -WIRE 48 320 0 320 -WIRE -288 400 -336 400 -WIRE 96 400 96 336 -WIRE 96 400 -208 400 -WIRE -336 432 -336 400 -FLAG -336 432 0 -FLAG -336 -128 0 -FLAG -208 96 A -IOPIN -208 96 In -FLAG 256 96 Y -IOPIN 256 96 Out -SYMBOL pmos 48 0 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL nmos 48 240 R0 -SYMATTR InstName M2 -SYMATTR Value N-ELOW -SYMBOL voltage -192 -160 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -192 400 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -TEXT 408 -160 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 924 680 +WIRE -288 -160 -336 -160 +WIRE 96 -160 -208 -160 +WIRE -336 -128 -336 -160 +WIRE 96 -96 96 -160 +WIRE 48 -80 0 -80 +WIRE 0 96 0 -80 +WIRE 0 96 -208 96 +WIRE 96 96 96 0 +WIRE 256 96 96 96 +WIRE 96 240 96 96 +WIRE 0 320 0 96 +WIRE 48 320 0 320 +WIRE -288 400 -336 400 +WIRE 96 400 96 336 +WIRE 96 400 -208 400 +WIRE -336 432 -336 400 +FLAG -336 432 0 +FLAG -336 -128 0 +FLAG -208 96 A +IOPIN -208 96 In +FLAG 256 96 Y +IOPIN 256 96 Out +SYMBOL pmos 48 0 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL nmos 48 240 R0 +SYMATTR InstName M2 +SYMATTR Value N-ELOW +SYMBOL voltage -192 -160 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -192 400 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +TEXT 408 -160 Left 0 !.inc ./custom.mos diff --git a/CMOS/negative_threshold_inverter.asy b/CMOS/negative_threshold_inverter.asy index 91e3aad..3e4e735 100644 --- a/CMOS/negative_threshold_inverter.asy +++ b/CMOS/negative_threshold_inverter.asy @@ -1,18 +1,18 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -TEXT 0 48 Center 0 NTI -SYMATTR Description Negative threshold inverter -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 NTI +SYMATTR Description Negative threshold inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/positive_threshold_inverter.asc b/CMOS/positive_threshold_inverter.asc index 1d0c1c5..25ccd49 100644 --- a/CMOS/positive_threshold_inverter.asc +++ b/CMOS/positive_threshold_inverter.asc @@ -1,45 +1,45 @@ -Version 4 -SHEET 1 924 680 -WIRE -288 -160 -336 -160 -WIRE 96 -160 -208 -160 -WIRE -336 -128 -336 -160 -WIRE 96 -96 96 -160 -WIRE 48 -80 0 -80 -WIRE 0 96 0 -80 -WIRE 0 96 -208 96 -WIRE 96 96 96 0 -WIRE 256 96 96 96 -WIRE 96 240 96 96 -WIRE 0 320 0 96 -WIRE 48 320 0 320 -WIRE -288 400 -336 400 -WIRE 96 400 96 336 -WIRE 96 400 -208 400 -WIRE -336 432 -336 400 -FLAG -336 432 0 -FLAG -336 -128 0 -FLAG -208 96 A -IOPIN -208 96 In -FLAG 256 96 Y -IOPIN 256 96 Out -SYMBOL pmos 48 0 M180 -SYMATTR InstName M1 -SYMATTR Value P-ELOW -SYMBOL nmos 48 240 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL voltage -192 -160 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -192 400 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -TEXT 408 -160 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 924 680 +WIRE -288 -160 -336 -160 +WIRE 96 -160 -208 -160 +WIRE -336 -128 -336 -160 +WIRE 96 -96 96 -160 +WIRE 48 -80 0 -80 +WIRE 0 96 0 -80 +WIRE 0 96 -208 96 +WIRE 96 96 96 0 +WIRE 256 96 96 96 +WIRE 96 240 96 96 +WIRE 0 320 0 96 +WIRE 48 320 0 320 +WIRE -288 400 -336 400 +WIRE 96 400 96 336 +WIRE 96 400 -208 400 +WIRE -336 432 -336 400 +FLAG -336 432 0 +FLAG -336 -128 0 +FLAG -208 96 A +IOPIN -208 96 In +FLAG 256 96 Y +IOPIN 256 96 Out +SYMBOL pmos 48 0 M180 +SYMATTR InstName M1 +SYMATTR Value P-ELOW +SYMBOL nmos 48 240 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL voltage -192 -160 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -192 400 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +TEXT 408 -160 Left 0 !.inc ./custom.mos diff --git a/CMOS/positive_threshold_inverter.asy b/CMOS/positive_threshold_inverter.asy index 1122cb4..3ce48e9 100644 --- a/CMOS/positive_threshold_inverter.asy +++ b/CMOS/positive_threshold_inverter.asy @@ -1,18 +1,18 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -TEXT 0 48 Center 0 PTI -SYMATTR Description Positive threshold inverter -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 PTI +SYMATTR Description Positive threshold inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/CMOS/standard_inverter.asc b/CMOS/standard_inverter.asc index c48a2c7..5f64dd3 100644 --- a/CMOS/standard_inverter.asc +++ b/CMOS/standard_inverter.asc @@ -1,63 +1,63 @@ -Version 4 -SHEET 1 924 680 -WIRE -288 -160 -336 -160 -WIRE 96 -160 -208 -160 -WIRE -336 -128 -336 -160 -WIRE 96 -96 96 -160 -WIRE 48 -80 0 -80 -WIRE -80 96 -208 96 -WIRE 0 96 0 -80 -WIRE 0 96 -80 96 -WIRE 96 96 96 0 -WIRE 480 96 96 96 -WIRE 640 96 480 96 -WIRE 480 144 480 96 -WIRE 432 224 384 224 -WIRE 96 240 96 96 -WIRE 480 272 480 240 -WIRE 0 320 0 96 -WIRE 48 320 0 320 -WIRE 384 352 384 224 -WIRE 432 352 384 352 -WIRE -288 400 -336 400 -WIRE 96 400 96 336 -WIRE 96 400 -208 400 -WIRE -336 432 -336 400 -WIRE 480 432 480 368 -WIRE -80 464 -80 96 -WIRE 384 464 384 352 -WIRE 384 464 -80 464 -FLAG 480 432 0 -FLAG -336 432 0 -FLAG -336 -128 0 -FLAG -208 96 A -IOPIN -208 96 In -FLAG 640 96 Y -IOPIN 640 96 Out -SYMBOL pmos 48 0 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL nmos 48 240 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL nmos 432 272 R0 -SYMATTR InstName M3 -SYMATTR Value N-DLOW -SYMBOL pmos 432 144 R0 -SYMATTR InstName M4 -SYMATTR Value P-DLOW -SYMBOL voltage -192 -160 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -192 400 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -TEXT 408 -160 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 924 680 +WIRE -288 -160 -336 -160 +WIRE 96 -160 -208 -160 +WIRE -336 -128 -336 -160 +WIRE 96 -96 96 -160 +WIRE 48 -80 0 -80 +WIRE -80 96 -208 96 +WIRE 0 96 0 -80 +WIRE 0 96 -80 96 +WIRE 96 96 96 0 +WIRE 480 96 96 96 +WIRE 640 96 480 96 +WIRE 480 144 480 96 +WIRE 432 224 384 224 +WIRE 96 240 96 96 +WIRE 480 272 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16 560 -WIRE -224 608 -224 560 -WIRE 1184 608 1184 368 -WIRE 1184 608 -224 608 -WIRE -432 640 -480 640 -WIRE -80 640 -80 576 -WIRE -80 640 -352 640 -WIRE 176 640 176 576 -WIRE 176 640 -80 640 -WIRE -480 672 -480 640 -FLAG -480 -192 0 -FLAG -480 672 0 -FLAG 736 512 0 -FLAG 1280 512 0 -FLAG -560 48 A -IOPIN -560 48 In -FLAG -560 368 B -IOPIN -560 368 In -FLAG 1392 -112 Y -IOPIN 1392 -112 Out -SYMBOL pmos -128 -64 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos -128 128 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL pmos 128 -64 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL pmos 128 128 M180 -SYMATTR InstName M4 -SYMATTR Value P-ENH -SYMBOL nmos -128 288 R0 -SYMATTR InstName M5 -SYMATTR Value N-ENH -SYMBOL nmos -128 480 R0 -SYMATTR InstName M6 -SYMATTR Value N-ENH -SYMBOL nmos 128 288 R0 -SYMATTR InstName M7 -SYMATTR Value N-ENH -SYMBOL nmos 128 480 R0 -SYMATTR InstName M8 -SYMATTR Value N-ENH -SYMBOL voltage -336 -224 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -336 640 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -SYMBOL nmos 688 32 R0 -SYMATTR InstName M9 -SYMATTR Value N-DLOW -SYMBOL nmos 416 32 R0 -SYMATTR InstName M10 -SYMATTR Value N-DLOW -SYMBOL pmos 416 288 R0 -SYMATTR InstName M11 -SYMATTR Value P-DLOW -SYMBOL pmos 688 288 R0 -SYMATTR InstName M12 -SYMATTR Value P-DLOW -SYMBOL standard_inverter -384 0 R0 -SYMATTR InstName X1 -SYMBOL standard_inverter -384 320 R0 -SYMATTR InstName X2 -SYMBOL nmos 960 32 R0 -SYMATTR InstName M13 -SYMATTR Value N-DLOW -SYMBOL nmos 1232 32 R0 -SYMATTR InstName M14 -SYMATTR Value N-DLOW -SYMBOL pmos 960 288 R0 -SYMATTR InstName M15 -SYMATTR Value P-DLOW -SYMBOL pmos 1232 288 R0 -SYMATTR InstName M16 -SYMATTR Value P-DLOW -TEXT -64 -296 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 1472 724 +WIRE -432 -224 -480 -224 +WIRE -80 -224 -352 -224 +WIRE 176 -224 -80 -224 +WIRE -480 -192 -480 -224 +WIRE -80 -160 -80 -224 +WIRE 176 -160 176 -224 +WIRE -128 -144 -176 -144 +WIRE 128 -144 80 -144 +WIRE 464 -112 272 -112 +WIRE 1008 -112 464 -112 +WIRE 1392 -112 1008 -112 +WIRE -176 -48 -176 -144 +WIRE -176 -48 -480 -48 +WIRE 16 -48 -176 -48 +WIRE 368 -48 16 -48 +WIRE 736 -48 576 -48 +WIRE 1280 -48 1120 -48 +WIRE 80 0 80 -144 +WIRE 80 0 -272 0 +WIRE 640 0 80 0 +WIRE -80 32 -80 -64 +WIRE 176 32 176 -64 +WIRE 464 32 464 -112 +WIRE 736 32 736 -48 +WIRE 1008 32 1008 -112 +WIRE 1280 32 1280 -48 +WIRE -480 48 -480 -48 +WIRE -480 48 -560 48 +WIRE -432 48 -480 48 +WIRE -272 48 -272 0 +WIRE -272 48 -320 48 +WIRE -128 48 -224 48 +WIRE 128 48 80 48 +WIRE 368 112 368 -48 +WIRE 416 112 368 112 +WIRE 640 112 640 0 +WIRE 688 112 640 112 +WIRE 960 112 912 112 +WIRE 1232 112 1184 112 +WIRE -272 208 -272 48 +WIRE -176 208 -272 208 +WIRE -80 208 -80 128 +WIRE 176 208 176 128 +WIRE 176 208 -80 208 +WIRE 272 208 272 -112 +WIRE 272 208 176 208 +WIRE -80 288 -80 208 +WIRE 176 288 176 208 +WIRE 464 288 464 128 +WIRE 736 288 736 128 +WIRE 1008 288 1008 128 +WIRE 1280 288 1280 128 +WIRE -480 368 -560 368 +WIRE -432 368 -480 368 +WIRE -224 368 -224 48 +WIRE -224 368 -320 368 +WIRE -176 368 -176 208 +WIRE -128 368 -176 368 +WIRE 80 368 80 48 +WIRE 128 368 80 368 +WIRE 368 368 368 112 +WIRE 416 368 368 368 +WIRE 640 368 640 112 +WIRE 688 368 640 368 +WIRE 912 368 912 112 +WIRE 960 368 912 368 +WIRE 1184 368 1184 112 +WIRE 1232 368 1184 368 +WIRE 464 416 464 384 +WIRE 576 416 576 -48 +WIRE 576 416 464 416 +WIRE 1008 416 1008 384 +WIRE 1120 416 1120 -48 +WIRE 1120 416 1008 416 +WIRE -480 464 -480 368 +WIRE 80 464 80 368 +WIRE 80 464 -480 464 +WIRE 912 464 912 368 +WIRE 912 464 80 464 +WIRE -80 480 -80 384 +WIRE 176 480 176 384 +WIRE 736 512 736 384 +WIRE 1280 512 1280 384 +WIRE -224 560 -224 368 +WIRE -128 560 -224 560 +WIRE 16 560 16 -48 +WIRE 128 560 16 560 +WIRE -224 608 -224 560 +WIRE 1184 608 1184 368 +WIRE 1184 608 -224 608 +WIRE -432 640 -480 640 +WIRE -80 640 -80 576 +WIRE -80 640 -352 640 +WIRE 176 640 176 576 +WIRE 176 640 -80 640 +WIRE -480 672 -480 640 +FLAG -480 -192 0 +FLAG -480 672 0 +FLAG 736 512 0 +FLAG 1280 512 0 +FLAG -560 48 A +IOPIN -560 48 In +FLAG -560 368 B +IOPIN -560 368 In +FLAG 1392 -112 Y +IOPIN 1392 -112 Out +SYMBOL pmos -128 -64 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos -128 128 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL pmos 128 -64 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL pmos 128 128 M180 +SYMATTR InstName M4 +SYMATTR Value P-ENH +SYMBOL nmos -128 288 R0 +SYMATTR InstName M5 +SYMATTR Value N-ENH +SYMBOL nmos -128 480 R0 +SYMATTR InstName M6 +SYMATTR Value N-ENH +SYMBOL nmos 128 288 R0 +SYMATTR InstName M7 +SYMATTR Value N-ENH +SYMBOL nmos 128 480 R0 +SYMATTR InstName M8 +SYMATTR Value N-ENH +SYMBOL voltage -336 -224 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -336 640 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +SYMBOL nmos 688 32 R0 +SYMATTR InstName M9 +SYMATTR Value N-DLOW +SYMBOL nmos 416 32 R0 +SYMATTR InstName M10 +SYMATTR Value N-DLOW +SYMBOL pmos 416 288 R0 +SYMATTR InstName M11 +SYMATTR Value P-DLOW +SYMBOL pmos 688 288 R0 +SYMATTR InstName M12 +SYMATTR Value P-DLOW +SYMBOL standard_inverter -384 0 R0 +SYMATTR InstName X1 +SYMBOL standard_inverter -384 320 R0 +SYMATTR InstName X2 +SYMBOL nmos 960 32 R0 +SYMATTR InstName M13 +SYMATTR Value N-DLOW +SYMBOL nmos 1232 32 R0 +SYMATTR InstName M14 +SYMATTR Value N-DLOW +SYMBOL pmos 960 288 R0 +SYMATTR InstName M15 +SYMATTR Value P-DLOW +SYMBOL pmos 1232 288 R0 +SYMATTR InstName M16 +SYMATTR Value P-DLOW +TEXT -64 -296 Left 0 !.inc ./custom.mos diff --git a/CMOS/xor.asy b/CMOS/xor.asy index bdf30a2..c454326 100644 --- a/CMOS/xor.asy +++ b/CMOS/xor.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 XOR -SYMATTR Description XOR gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 XOR +SYMATTR Description XOR gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/antimax.asc b/RMOS/antimax.asc index 5119b84..0a6c8ee 100644 --- a/RMOS/antimax.asc +++ b/RMOS/antimax.asc @@ -1,74 +1,74 @@ -Version 4 -SHEET 1 880 680 -WIRE -176 -192 -208 -192 -WIRE 176 -192 -96 -192 -WIRE -208 -160 -208 -192 -WIRE 176 -160 176 -192 -WIRE 128 -144 96 -144 -WIRE 176 -32 176 -64 -WIRE 128 -16 -32 -16 -WIRE -32 16 -32 -16 -WIRE -32 16 -176 16 -WIRE 176 192 176 64 -WIRE 480 192 176 192 -WIRE 608 192 480 192 -WIRE 96 208 96 -144 -WIRE 96 208 -176 208 -WIRE 480 224 480 192 -WIRE 176 320 176 192 -WIRE 176 320 64 320 -WIRE 288 320 176 320 -WIRE 64 352 64 320 -WIRE 288 352 288 320 -WIRE 96 368 96 208 -WIRE 192 368 96 368 -WIRE 480 368 480 304 -WIRE -32 432 -32 16 -WIRE 16 432 -32 432 -WIRE 192 432 192 368 -WIRE 240 432 192 432 -WIRE -176 480 -208 480 -WIRE 64 480 64 448 -WIRE 64 480 -96 480 -WIRE 288 480 288 448 -WIRE 288 480 64 480 -WIRE -208 512 -208 480 -FLAG -208 -160 0 -FLAG 480 368 0 -FLAG -208 512 0 -FLAG -176 16 A -IOPIN -176 16 In -FLAG -176 208 B -IOPIN -176 208 In -FLAG 608 192 Y -IOPIN 608 192 Out -SYMBOL pmos 128 -64 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos 128 64 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL nmos 16 352 R0 -SYMATTR InstName M3 -SYMATTR Value N-ENH -SYMBOL nmos 240 352 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL res 464 208 R0 -SYMATTR InstName R2 -SYMATTR Value 12k -SYMBOL voltage -80 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -80 480 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT 336 -96 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -176 -192 -208 -192 +WIRE 176 -192 -96 -192 +WIRE -208 -160 -208 -192 +WIRE 176 -160 176 -192 +WIRE 128 -144 96 -144 +WIRE 176 -32 176 -64 +WIRE 128 -16 -32 -16 +WIRE -32 16 -32 -16 +WIRE -32 16 -176 16 +WIRE 176 192 176 64 +WIRE 480 192 176 192 +WIRE 608 192 480 192 +WIRE 96 208 96 -144 +WIRE 96 208 -176 208 +WIRE 480 224 480 192 +WIRE 176 320 176 192 +WIRE 176 320 64 320 +WIRE 288 320 176 320 +WIRE 64 352 64 320 +WIRE 288 352 288 320 +WIRE 96 368 96 208 +WIRE 192 368 96 368 +WIRE 480 368 480 304 +WIRE -32 432 -32 16 +WIRE 16 432 -32 432 +WIRE 192 432 192 368 +WIRE 240 432 192 432 +WIRE -176 480 -208 480 +WIRE 64 480 64 448 +WIRE 64 480 -96 480 +WIRE 288 480 288 448 +WIRE 288 480 64 480 +WIRE -208 512 -208 480 +FLAG -208 -160 0 +FLAG 480 368 0 +FLAG -208 512 0 +FLAG -176 16 A +IOPIN -176 16 In +FLAG -176 208 B +IOPIN -176 208 In +FLAG 608 192 Y +IOPIN 608 192 Out +SYMBOL pmos 128 -64 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos 128 64 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL nmos 16 352 R0 +SYMATTR InstName M3 +SYMATTR Value N-ENH +SYMBOL nmos 240 352 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL res 464 208 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +SYMBOL voltage -80 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -80 480 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT 336 -96 Left 0 !.inc ./custom.mos diff --git a/RMOS/antimax.asy b/RMOS/antimax.asy index e29234c..8ef0d80 100644 --- a/RMOS/antimax.asy +++ b/RMOS/antimax.asy @@ -1,24 +1,24 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 56 48 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 77 Center 0 MAX -TEXT 0 52 Center 0 ANTI -SYMATTR Description 2-input ANTIMAX gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 77 Center 0 MAX +TEXT 0 52 Center 0 ANTI +SYMATTR Description 2-input ANTIMAX gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/antimin.asc b/RMOS/antimin.asc index 6dbf8c8..4647239 100644 --- a/RMOS/antimin.asc +++ b/RMOS/antimin.asc @@ -1,74 +1,74 @@ -Version 4 -SHEET 1 880 680 -WIRE -320 -176 -352 -176 -WIRE -96 -176 -240 -176 -WIRE 176 -176 -96 -176 -WIRE -352 -144 -352 -176 -WIRE -96 -144 -96 -176 -WIRE 176 -144 176 -176 -WIRE -144 -128 -176 -128 -WIRE 128 -128 48 -128 -WIRE 48 -48 48 -128 -WIRE 48 -48 -32 -48 -WIRE -96 -16 -96 -48 -WIRE 48 -16 -96 -16 -WIRE 176 -16 176 -48 -WIRE 176 -16 48 -16 -WIRE -176 48 -176 -128 -WIRE -176 48 -272 48 -WIRE 48 112 48 -16 -WIRE 256 112 48 112 -WIRE 384 112 256 112 -WIRE 256 160 256 112 -WIRE -32 192 -32 -48 -WIRE -32 192 -272 192 -WIRE 48 240 48 112 -WIRE -32 320 -32 192 -WIRE 0 320 -32 320 -WIRE 256 320 256 240 -WIRE 48 368 48 336 -WIRE -176 448 -176 48 -WIRE 0 448 -176 448 -WIRE -320 496 -352 496 -WIRE 48 496 48 464 -WIRE 48 496 -240 496 -WIRE -352 528 -352 496 -FLAG -352 528 0 -FLAG 256 320 0 -FLAG -352 -144 0 -FLAG -272 48 A -IOPIN -272 48 In -FLAG -272 192 B -IOPIN -272 192 In -FLAG 384 112 Y -IOPIN 384 112 Out -SYMBOL pmos -144 -48 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos 128 -48 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL nmos 0 240 R0 -SYMATTR InstName M3 -SYMATTR Value N-ENH -SYMBOL nmos 0 368 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL res 240 144 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -224 -176 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -224 496 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V4 -SYMATTR Value -1 -TEXT 312 -152 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -320 -176 -352 -176 +WIRE -96 -176 -240 -176 +WIRE 176 -176 -96 -176 +WIRE -352 -144 -352 -176 +WIRE -96 -144 -96 -176 +WIRE 176 -144 176 -176 +WIRE -144 -128 -176 -128 +WIRE 128 -128 48 -128 +WIRE 48 -48 48 -128 +WIRE 48 -48 -32 -48 +WIRE -96 -16 -96 -48 +WIRE 48 -16 -96 -16 +WIRE 176 -16 176 -48 +WIRE 176 -16 48 -16 +WIRE -176 48 -176 -128 +WIRE -176 48 -272 48 +WIRE 48 112 48 -16 +WIRE 256 112 48 112 +WIRE 384 112 256 112 +WIRE 256 160 256 112 +WIRE -32 192 -32 -48 +WIRE -32 192 -272 192 +WIRE 48 240 48 112 +WIRE -32 320 -32 192 +WIRE 0 320 -32 320 +WIRE 256 320 256 240 +WIRE 48 368 48 336 +WIRE -176 448 -176 48 +WIRE 0 448 -176 448 +WIRE -320 496 -352 496 +WIRE 48 496 48 464 +WIRE 48 496 -240 496 +WIRE -352 528 -352 496 +FLAG -352 528 0 +FLAG 256 320 0 +FLAG -352 -144 0 +FLAG -272 48 A +IOPIN -272 48 In +FLAG -272 192 B +IOPIN -272 192 In +FLAG 384 112 Y +IOPIN 384 112 Out +SYMBOL pmos -144 -48 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos 128 -48 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL nmos 0 240 R0 +SYMATTR InstName M3 +SYMATTR Value N-ENH +SYMBOL nmos 0 368 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL res 240 144 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -224 -176 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -224 496 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value -1 +TEXT 312 -152 Left 0 !.inc ./custom.mos diff --git a/RMOS/antimin.asy b/RMOS/antimin.asy index 1b33509..2e9850b 100644 --- a/RMOS/antimin.asy +++ b/RMOS/antimin.asy @@ -1,24 +1,24 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 56 48 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 77 Center 0 MIN -TEXT 0 52 Center 0 ANTI -SYMATTR Description 2-input ANTIMIN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 77 Center 0 MIN +TEXT 0 52 Center 0 ANTI +SYMATTR Description 2-input ANTIMIN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/buffer.asc b/RMOS/buffer.asc index 56e5566..c390ea3 100644 --- a/RMOS/buffer.asc +++ b/RMOS/buffer.asc @@ -1,12 +1,12 @@ -Version 4 -SHEET 1 880 680 -WIRE 80 144 48 144 -WIRE 336 144 304 144 -FLAG 48 144 A -IOPIN 48 144 In -FLAG 336 144 Y -IOPIN 336 144 Out -SYMBOL .\\standard_inverter 128 96 R0 -SYMATTR InstName X1 -SYMBOL .\\standard_inverter 240 96 R0 -SYMATTR InstName X2 +Version 4 +SHEET 1 880 680 +WIRE 80 144 48 144 +WIRE 336 144 304 144 +FLAG 48 144 A +IOPIN 48 144 In +FLAG 336 144 Y +IOPIN 336 144 Out +SYMBOL .\\standard_inverter 128 96 R0 +SYMATTR InstName X1 +SYMBOL .\\standard_inverter 240 96 R0 +SYMATTR InstName X2 diff --git a/RMOS/buffer.asy b/RMOS/buffer.asy index e92d13d..a659405 100644 --- a/RMOS/buffer.asy +++ b/RMOS/buffer.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 BUF -SYMATTR Description Buffer -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 BUF +SYMATTR Description Buffer +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/clamp_down.asc b/RMOS/clamp_down.asc index a2ea7fc..b972fb3 100644 --- a/RMOS/clamp_down.asc +++ b/RMOS/clamp_down.asc @@ -1,60 +1,60 @@ -Version 4 -SHEET 1 880 680 -WIRE -176 -112 -208 -112 -WIRE 48 -112 -96 -112 -WIRE 320 -112 272 -112 -WIRE -208 -80 -208 -112 -WIRE 48 -80 48 -112 -WIRE 272 -80 272 -112 -WIRE 0 -64 -64 -64 -WIRE 320 -64 320 -112 -WIRE -64 80 -64 -64 -WIRE -64 80 -176 80 -WIRE 48 80 48 16 -WIRE 208 80 48 80 -WIRE 320 80 320 16 -WIRE 496 80 320 80 -WIRE 48 144 48 80 -WIRE 320 144 320 80 -WIRE 208 224 208 80 -WIRE 272 224 208 224 -WIRE 48 272 48 224 -WIRE -176 336 -208 336 -WIRE 320 336 320 240 -WIRE 320 336 -96 336 -WIRE -208 368 -208 336 -FLAG 272 -80 0 -FLAG 48 272 0 -FLAG -208 -80 0 -FLAG -208 368 0 -FLAG -176 80 A -IOPIN -176 80 In -FLAG 496 80 Y -IOPIN 496 80 Out -SYMBOL pmos 0 16 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL res 32 128 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL nmos 272 144 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL res 304 -80 R0 -SYMATTR InstName R2 -SYMATTR Value 12k -SYMBOL voltage -80 -112 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -80 336 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT 80 384 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -176 -112 -208 -112 +WIRE 48 -112 -96 -112 +WIRE 320 -112 272 -112 +WIRE -208 -80 -208 -112 +WIRE 48 -80 48 -112 +WIRE 272 -80 272 -112 +WIRE 0 -64 -64 -64 +WIRE 320 -64 320 -112 +WIRE -64 80 -64 -64 +WIRE -64 80 -176 80 +WIRE 48 80 48 16 +WIRE 208 80 48 80 +WIRE 320 80 320 16 +WIRE 496 80 320 80 +WIRE 48 144 48 80 +WIRE 320 144 320 80 +WIRE 208 224 208 80 +WIRE 272 224 208 224 +WIRE 48 272 48 224 +WIRE -176 336 -208 336 +WIRE 320 336 320 240 +WIRE 320 336 -96 336 +WIRE -208 368 -208 336 +FLAG 272 -80 0 +FLAG 48 272 0 +FLAG -208 -80 0 +FLAG -208 368 0 +FLAG -176 80 A +IOPIN -176 80 In +FLAG 496 80 Y +IOPIN 496 80 Out +SYMBOL pmos 0 16 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL res 32 128 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL nmos 272 144 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL res 304 -80 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +SYMBOL voltage -80 -112 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -80 336 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT 80 384 Left 0 !.inc ./custom.mos diff --git a/RMOS/clamp_down.asy b/RMOS/clamp_down.asy index 3fccbd7..cc88457 100644 --- a/RMOS/clamp_down.asy +++ b/RMOS/clamp_down.asy @@ -1,20 +1,20 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MIN -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP DOWN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MIN +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP DOWN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/clamp_up.asc b/RMOS/clamp_up.asc index 4b811f0..83d7600 100644 --- a/RMOS/clamp_up.asc +++ b/RMOS/clamp_up.asc @@ -1,60 +1,60 @@ -Version 4 -SHEET 1 880 680 -WIRE -128 -192 -160 -192 -WIRE 320 -192 -48 -192 -WIRE -160 -160 -160 -192 -WIRE 80 -144 32 -144 -WIRE 32 -112 32 -144 -WIRE 320 -112 320 -192 -WIRE 80 -96 80 -144 -WIRE 272 -96 224 -96 -WIRE -16 64 -128 64 -WIRE 80 64 80 -16 -WIRE 224 64 224 -96 -WIRE 224 64 80 64 -WIRE 320 64 320 -16 -WIRE 448 64 320 64 -WIRE 80 144 80 64 -WIRE 320 144 320 64 -WIRE -16 224 -16 64 -WIRE 32 224 -16 224 -WIRE -128 288 -160 288 -WIRE 80 288 80 240 -WIRE 80 288 -48 288 -WIRE 320 288 320 224 -WIRE -160 320 -160 288 -FLAG -160 320 0 -FLAG 32 -112 0 -FLAG -160 -160 0 -FLAG 320 288 0 -FLAG -128 64 A -IOPIN -128 64 In -FLAG 448 64 Y -IOPIN 448 64 Out -SYMBOL nmos 32 144 R0 -SYMATTR InstName M1 -SYMATTR Value N-ENH -SYMBOL res 64 -112 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -32 288 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -SYMBOL pmos 272 -16 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL voltage -32 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value 1 -SYMBOL res 304 128 R0 -SYMATTR InstName R2 -SYMATTR Value 12k -TEXT -312 -80 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -128 -192 -160 -192 +WIRE 320 -192 -48 -192 +WIRE -160 -160 -160 -192 +WIRE 80 -144 32 -144 +WIRE 32 -112 32 -144 +WIRE 320 -112 320 -192 +WIRE 80 -96 80 -144 +WIRE 272 -96 224 -96 +WIRE -16 64 -128 64 +WIRE 80 64 80 -16 +WIRE 224 64 224 -96 +WIRE 224 64 80 64 +WIRE 320 64 320 -16 +WIRE 448 64 320 64 +WIRE 80 144 80 64 +WIRE 320 144 320 64 +WIRE -16 224 -16 64 +WIRE 32 224 -16 224 +WIRE -128 288 -160 288 +WIRE 80 288 80 240 +WIRE 80 288 -48 288 +WIRE 320 288 320 224 +WIRE -160 320 -160 288 +FLAG -160 320 0 +FLAG 32 -112 0 +FLAG -160 -160 0 +FLAG 320 288 0 +FLAG -128 64 A +IOPIN -128 64 In +FLAG 448 64 Y +IOPIN 448 64 Out +SYMBOL nmos 32 144 R0 +SYMATTR InstName M1 +SYMATTR Value N-ENH +SYMBOL res 64 -112 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -32 288 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +SYMBOL pmos 272 -16 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL voltage -32 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value 1 +SYMBOL res 304 128 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +TEXT -312 -80 Left 0 !.inc ./custom.mos diff --git a/RMOS/clamp_up.asy b/RMOS/clamp_up.asy index b4ebc93..5504d00 100644 --- a/RMOS/clamp_up.asy +++ b/RMOS/clamp_up.asy @@ -1,20 +1,20 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MAX -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP UP gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MAX +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP UP gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/consensus.asc b/RMOS/consensus.asc index 909aea7..55bb664 100644 --- a/RMOS/consensus.asc +++ b/RMOS/consensus.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 64 144 32 144 -WIRE 320 160 288 160 -WIRE 64 176 32 176 -FLAG 32 144 A -IOPIN 32 144 In -FLAG 32 176 B -IOPIN 32 176 In -FLAG 320 160 Y -IOPIN 320 160 Out -SYMBOL .\\inverting_consensus 112 96 R0 -SYMATTR InstName X1 -SYMBOL .\\standard_inverter 224 112 R0 -SYMATTR InstName X2 +Version 4 +SHEET 1 880 680 +WIRE 64 144 32 144 +WIRE 320 160 288 160 +WIRE 64 176 32 176 +FLAG 32 144 A +IOPIN 32 144 In +FLAG 32 176 B +IOPIN 32 176 In +FLAG 320 160 Y +IOPIN 320 160 Out +SYMBOL .\\inverting_consensus 112 96 R0 +SYMATTR InstName X1 +SYMBOL .\\standard_inverter 224 112 R0 +SYMATTR InstName X2 diff --git a/RMOS/consensus.asy b/RMOS/consensus.asy index 1201fa4..b7aff7d 100644 --- a/RMOS/consensus.asy +++ b/RMOS/consensus.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 CON -SYMATTR Description 2-input consensus gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 CON +SYMATTR Description 2-input consensus gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/custom.mos b/RMOS/custom.mos index 9f38457..d63d327 100644 --- a/RMOS/custom.mos +++ b/RMOS/custom.mos @@ -1,24 +1,24 @@ -.model P-DEP VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - -.model N-DEP VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) - - - -.model P-DLOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - -.model N-DLOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) - - - - - - -.model P-ENH VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - -.model N-ENH VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) - - - -.model P-ELOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) - +.model P-DEP VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + +.model N-DEP VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) + + + +.model P-DLOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + +.model N-DLOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) + + + + + + +.model P-ENH VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + +.model N-ENH VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) + + + +.model P-ELOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n) + .model N-ELOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n) \ No newline at end of file diff --git a/RMOS/decrement.asc b/RMOS/decrement.asc index 9ff6525..ade3911 100644 --- a/RMOS/decrement.asc +++ b/RMOS/decrement.asc @@ -1,59 +1,59 @@ -Version 4 -SHEET 1 880 680 -WIRE -192 -192 -224 -192 -WIRE 16 -192 -112 -192 -WIRE -224 -160 -224 -192 -WIRE 16 -128 16 -192 -WIRE -32 -112 -80 -112 -WIRE -80 32 -80 -112 -WIRE -80 32 -192 32 -WIRE 16 32 16 -32 -WIRE 176 32 16 32 -WIRE 304 32 176 32 -WIRE 16 96 16 32 -WIRE 176 96 176 32 -WIRE 16 208 16 176 -WIRE 176 208 176 176 -WIRE -80 288 -80 32 -WIRE -32 288 -80 288 -WIRE 128 288 80 288 -WIRE -192 352 -224 352 -WIRE 176 352 176 304 -WIRE 176 352 -112 352 -WIRE -224 384 -224 352 -FLAG 16 208 0 -FLAG -224 -160 0 -FLAG -224 384 0 -FLAG -192 32 A -IOPIN -192 32 In -FLAG 304 32 Y -IOPIN 304 32 Out -SYMBOL pmos -32 -32 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL nmos 128 208 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL res 0 80 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -96 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value 1 -SYMBOL res 160 80 R0 -SYMATTR InstName R2 -SYMATTR Value 100 -SYMBOL voltage -96 352 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V4 -SYMATTR Value -1 -SYMBOL .\\positive_threshold_inverter 16 240 R0 -SYMATTR InstName X1 -TEXT 160 -96 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -192 -192 -224 -192 +WIRE 16 -192 -112 -192 +WIRE -224 -160 -224 -192 +WIRE 16 -128 16 -192 +WIRE -32 -112 -80 -112 +WIRE -80 32 -80 -112 +WIRE -80 32 -192 32 +WIRE 16 32 16 -32 +WIRE 176 32 16 32 +WIRE 304 32 176 32 +WIRE 16 96 16 32 +WIRE 176 96 176 32 +WIRE 16 208 16 176 +WIRE 176 208 176 176 +WIRE -80 288 -80 32 +WIRE -32 288 -80 288 +WIRE 128 288 80 288 +WIRE -192 352 -224 352 +WIRE 176 352 176 304 +WIRE 176 352 -112 352 +WIRE -224 384 -224 352 +FLAG 16 208 0 +FLAG -224 -160 0 +FLAG -224 384 0 +FLAG -192 32 A +IOPIN -192 32 In +FLAG 304 32 Y +IOPIN 304 32 Out +SYMBOL pmos -32 -32 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL nmos 128 208 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL res 0 80 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -96 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value 1 +SYMBOL res 160 80 R0 +SYMATTR InstName R2 +SYMATTR Value 100 +SYMBOL voltage -96 352 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value -1 +SYMBOL .\\positive_threshold_inverter 16 240 R0 +SYMATTR InstName X1 +TEXT 160 -96 Left 0 !.inc ./custom.mos diff --git a/RMOS/decrement.asy b/RMOS/decrement.asy index 3e3d8f7..4d5540b 100644 --- a/RMOS/decrement.asy +++ b/RMOS/decrement.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 -1 -SYMATTR Description Decrement gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 -1 +SYMATTR Description Decrement gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/equality.asc b/RMOS/equality.asc index 8f265d9..0f70c12 100644 --- a/RMOS/equality.asc +++ b/RMOS/equality.asc @@ -1,134 +1,134 @@ -Version 4 -SHEET 1 880 680 -WIRE 288 -352 208 -352 -WIRE 208 -320 208 -352 -WIRE 288 -304 288 -352 -WIRE 208 -208 208 -240 -WIRE -640 -96 -704 -96 -WIRE -224 -96 -528 -96 -WIRE 96 -96 -128 -96 -WIRE 208 -96 208 -128 -WIRE 208 -96 96 -96 -WIRE 320 -96 208 -96 -WIRE 544 -96 320 -96 -WIRE 704 -96 544 -96 -WIRE 416 -48 -272 -48 -WIRE -128 -32 -128 -96 -WIRE 96 -32 96 -96 -WIRE 320 -32 320 -96 -WIRE 544 -32 544 -96 -WIRE -704 48 -704 -96 -WIRE -704 48 -800 48 -WIRE -640 48 -704 48 -WIRE -480 48 -528 48 -WIRE -416 48 -480 48 -WIRE -272 48 -272 -48 -WIRE -272 48 -304 48 -WIRE -224 48 -224 -96 -WIRE -176 48 -224 48 -WIRE 48 48 0 48 -WIRE 272 48 224 48 -WIRE 496 48 464 48 -WIRE -704 96 -704 48 -WIRE 0 96 0 48 -WIRE 0 96 -704 96 -WIRE -480 144 -480 48 -WIRE 224 144 224 48 -WIRE 224 144 -480 144 -WIRE 464 192 464 48 -WIRE 464 192 -480 192 -WIRE -128 208 -128 64 -WIRE 96 208 96 64 -WIRE 320 208 320 64 -WIRE 544 208 544 64 -WIRE -224 240 -704 240 -WIRE -704 288 -704 240 -WIRE -704 288 -800 288 -WIRE -640 288 -704 288 -WIRE -480 288 -480 192 -WIRE -480 288 -528 288 -WIRE -416 288 -480 288 -WIRE -272 288 -304 288 -WIRE -224 288 -224 240 -WIRE -176 288 -224 288 -WIRE 48 288 0 288 -WIRE 272 288 224 288 -WIRE 416 288 416 -48 -WIRE 496 288 416 288 -WIRE -272 336 -272 288 -WIRE 224 336 224 288 -WIRE 224 336 -272 336 -WIRE -128 384 -128 304 -WIRE 96 384 96 304 -WIRE 96 384 -128 384 -WIRE 208 384 96 384 -WIRE 320 384 320 304 -WIRE 320 384 208 384 -WIRE 544 384 544 304 -WIRE 544 384 320 384 -WIRE -704 432 -704 288 -WIRE -640 432 -704 432 -WIRE 0 432 0 288 -WIRE 0 432 -528 432 -WIRE 208 432 208 384 -WIRE 208 560 208 512 -FLAG 208 560 0 -FLAG 288 -304 0 -FLAG -800 48 A -IOPIN -800 48 In -FLAG -800 288 B -IOPIN -800 288 In -FLAG 704 -96 Y -IOPIN 704 -96 Out -SYMBOL nmos -176 -32 R0 -SYMATTR InstName M1 -SYMATTR Value N-ENH -SYMBOL nmos -176 208 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL nmos 48 208 R0 -SYMATTR InstName M3 -SYMATTR Value N-ENH -SYMBOL nmos 272 208 R0 -SYMATTR InstName M4 -SYMATTR Value N-ENH -SYMBOL nmos 496 208 R0 -SYMATTR InstName M5 -SYMATTR Value N-ENH -SYMBOL nmos 48 -32 R0 -SYMATTR InstName M6 -SYMATTR Value N-ENH -SYMBOL nmos 272 -32 R0 -SYMATTR InstName M7 -SYMATTR Value N-ENH -SYMBOL nmos 496 -32 R0 -SYMATTR InstName M8 -SYMATTR Value N-ENH -SYMBOL res 192 -224 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage 208 416 R0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value -1 -SYMBOL voltage 208 -224 R180 -WINDOW 0 24 104 Left 0 -WINDOW 3 24 16 Left 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value 1 -SYMBOL .\\positive_threshold_inverter -592 -144 R0 -SYMATTR InstName X1 -SYMBOL .\\positive_threshold_inverter -368 0 R0 -SYMATTR InstName X2 -SYMBOL .\\positive_threshold_inverter -368 240 R0 -SYMATTR InstName X3 -SYMBOL .\\positive_threshold_inverter -592 384 R0 -SYMATTR InstName X4 -SYMBOL .\\negative_threshold_inverter -592 240 R0 -SYMATTR InstName X5 -SYMBOL .\\negative_threshold_inverter -592 0 R0 -SYMATTR InstName X6 -TEXT -224 -200 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE 288 -352 208 -352 +WIRE 208 -320 208 -352 +WIRE 288 -304 288 -352 +WIRE 208 -208 208 -240 +WIRE -640 -96 -704 -96 +WIRE -224 -96 -528 -96 +WIRE 96 -96 -128 -96 +WIRE 208 -96 208 -128 +WIRE 208 -96 96 -96 +WIRE 320 -96 208 -96 +WIRE 544 -96 320 -96 +WIRE 704 -96 544 -96 +WIRE 416 -48 -272 -48 +WIRE -128 -32 -128 -96 +WIRE 96 -32 96 -96 +WIRE 320 -32 320 -96 +WIRE 544 -32 544 -96 +WIRE -704 48 -704 -96 +WIRE -704 48 -800 48 +WIRE -640 48 -704 48 +WIRE -480 48 -528 48 +WIRE -416 48 -480 48 +WIRE -272 48 -272 -48 +WIRE -272 48 -304 48 +WIRE -224 48 -224 -96 +WIRE -176 48 -224 48 +WIRE 48 48 0 48 +WIRE 272 48 224 48 +WIRE 496 48 464 48 +WIRE -704 96 -704 48 +WIRE 0 96 0 48 +WIRE 0 96 -704 96 +WIRE -480 144 -480 48 +WIRE 224 144 224 48 +WIRE 224 144 -480 144 +WIRE 464 192 464 48 +WIRE 464 192 -480 192 +WIRE -128 208 -128 64 +WIRE 96 208 96 64 +WIRE 320 208 320 64 +WIRE 544 208 544 64 +WIRE -224 240 -704 240 +WIRE -704 288 -704 240 +WIRE -704 288 -800 288 +WIRE -640 288 -704 288 +WIRE -480 288 -480 192 +WIRE -480 288 -528 288 +WIRE -416 288 -480 288 +WIRE -272 288 -304 288 +WIRE -224 288 -224 240 +WIRE -176 288 -224 288 +WIRE 48 288 0 288 +WIRE 272 288 224 288 +WIRE 416 288 416 -48 +WIRE 496 288 416 288 +WIRE -272 336 -272 288 +WIRE 224 336 224 288 +WIRE 224 336 -272 336 +WIRE -128 384 -128 304 +WIRE 96 384 96 304 +WIRE 96 384 -128 384 +WIRE 208 384 96 384 +WIRE 320 384 320 304 +WIRE 320 384 208 384 +WIRE 544 384 544 304 +WIRE 544 384 320 384 +WIRE -704 432 -704 288 +WIRE -640 432 -704 432 +WIRE 0 432 0 288 +WIRE 0 432 -528 432 +WIRE 208 432 208 384 +WIRE 208 560 208 512 +FLAG 208 560 0 +FLAG 288 -304 0 +FLAG -800 48 A +IOPIN -800 48 In +FLAG -800 288 B +IOPIN -800 288 In +FLAG 704 -96 Y +IOPIN 704 -96 Out +SYMBOL nmos -176 -32 R0 +SYMATTR InstName M1 +SYMATTR Value N-ENH +SYMBOL nmos -176 208 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL nmos 48 208 R0 +SYMATTR InstName M3 +SYMATTR Value N-ENH +SYMBOL nmos 272 208 R0 +SYMATTR InstName M4 +SYMATTR Value N-ENH +SYMBOL nmos 496 208 R0 +SYMATTR InstName M5 +SYMATTR Value N-ENH +SYMBOL nmos 48 -32 R0 +SYMATTR InstName M6 +SYMATTR Value N-ENH +SYMBOL nmos 272 -32 R0 +SYMATTR InstName M7 +SYMATTR Value N-ENH +SYMBOL nmos 496 -32 R0 +SYMATTR InstName M8 +SYMATTR Value N-ENH +SYMBOL res 192 -224 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage 208 416 R0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value -1 +SYMBOL voltage 208 -224 R180 +WINDOW 0 24 104 Left 0 +WINDOW 3 24 16 Left 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value 1 +SYMBOL .\\positive_threshold_inverter -592 -144 R0 +SYMATTR InstName X1 +SYMBOL .\\positive_threshold_inverter -368 0 R0 +SYMATTR InstName X2 +SYMBOL .\\positive_threshold_inverter -368 240 R0 +SYMATTR InstName X3 +SYMBOL .\\positive_threshold_inverter -592 384 R0 +SYMATTR InstName X4 +SYMBOL .\\negative_threshold_inverter -592 240 R0 +SYMATTR InstName X5 +SYMBOL .\\negative_threshold_inverter -592 0 R0 +SYMATTR InstName X6 +TEXT -224 -200 Left 0 !.inc ./custom.mos diff --git a/RMOS/equality.asy b/RMOS/equality.asy index c6470ce..14fb10a 100644 --- a/RMOS/equality.asy +++ b/RMOS/equality.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 = -SYMATTR Description 2-input equality gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 = +SYMATTR Description 2-input equality gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/gullible.asc b/RMOS/gullible.asc index 04ebf33..3e15cfc 100644 --- a/RMOS/gullible.asc +++ b/RMOS/gullible.asc @@ -1,95 +1,95 @@ -Version 4 -SHEET 1 880 680 -WIRE -176 -288 -208 -288 -WIRE 32 -288 -96 -288 -WIRE -208 -256 -208 -288 -WIRE 32 -224 32 -288 -WIRE -16 -208 -144 -208 -WIRE -304 -128 -432 -128 -WIRE -144 -128 -144 -208 -WIRE -144 -128 -192 -128 -WIRE 32 -96 32 -128 -WIRE -16 -80 -96 -80 -WIRE -304 0 -368 0 -WIRE -48 0 -192 0 -WIRE 32 32 32 0 -WIRE -432 48 -432 -128 -WIRE -432 48 -496 48 -WIRE 32 128 32 112 -WIRE 208 128 32 128 -WIRE 336 128 208 128 -WIRE 32 144 32 128 -WIRE 208 192 208 128 -WIRE -368 208 -368 0 -WIRE -368 208 -496 208 -WIRE -432 256 -432 48 -WIRE -304 256 -432 256 -WIRE -144 256 -192 256 -WIRE 32 256 32 224 -WIRE 208 320 208 272 -WIRE -144 336 -144 256 -WIRE -16 336 -144 336 -WIRE -368 384 -368 208 -WIRE -304 384 -368 384 -WIRE -96 384 -96 -80 -WIRE -96 384 -192 384 -WIRE 32 384 32 352 -WIRE -48 464 -48 0 -WIRE -16 464 -48 464 -WIRE -176 544 -208 544 -WIRE 32 544 32 480 -WIRE 32 544 -96 544 -WIRE -208 576 -208 544 -FLAG 208 320 0 -FLAG -208 -256 0 -FLAG -208 576 0 -FLAG -496 48 A -IOPIN -496 48 In -FLAG -496 208 B -IOPIN -496 208 In -FLAG 336 128 Y -IOPIN 336 128 Out -SYMBOL nmos -16 256 R0 -SYMATTR InstName M1 -SYMATTR Value N-ENH -SYMBOL nmos -16 384 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL pmos -16 0 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL pmos -16 -128 M180 -SYMATTR InstName M4 -SYMATTR Value P-ENH -SYMBOL .\\positive_threshold_inverter -256 -48 R0 -SYMATTR InstName X1 -SYMBOL .\\positive_threshold_inverter -256 208 R0 -SYMATTR InstName X2 -SYMBOL .\\negative_threshold_inverter -256 -176 R0 -SYMATTR InstName X3 -SYMBOL .\\negative_threshold_inverter -256 336 R0 -SYMATTR InstName X4 -SYMBOL res 16 16 R0 -SYMATTR InstName R1 -SYMATTR Value 100 -SYMBOL res 16 128 R0 -SYMATTR InstName R2 -SYMATTR Value 100 -SYMBOL res 192 176 R0 -SYMATTR InstName R3 -SYMATTR Value 12k -SYMBOL voltage -80 -288 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -80 544 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT -424 -192 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -176 -288 -208 -288 +WIRE 32 -288 -96 -288 +WIRE -208 -256 -208 -288 +WIRE 32 -224 32 -288 +WIRE -16 -208 -144 -208 +WIRE -304 -128 -432 -128 +WIRE -144 -128 -144 -208 +WIRE -144 -128 -192 -128 +WIRE 32 -96 32 -128 +WIRE -16 -80 -96 -80 +WIRE -304 0 -368 0 +WIRE -48 0 -192 0 +WIRE 32 32 32 0 +WIRE -432 48 -432 -128 +WIRE -432 48 -496 48 +WIRE 32 128 32 112 +WIRE 208 128 32 128 +WIRE 336 128 208 128 +WIRE 32 144 32 128 +WIRE 208 192 208 128 +WIRE -368 208 -368 0 +WIRE -368 208 -496 208 +WIRE -432 256 -432 48 +WIRE -304 256 -432 256 +WIRE -144 256 -192 256 +WIRE 32 256 32 224 +WIRE 208 320 208 272 +WIRE -144 336 -144 256 +WIRE -16 336 -144 336 +WIRE -368 384 -368 208 +WIRE -304 384 -368 384 +WIRE -96 384 -96 -80 +WIRE -96 384 -192 384 +WIRE 32 384 32 352 +WIRE -48 464 -48 0 +WIRE -16 464 -48 464 +WIRE -176 544 -208 544 +WIRE 32 544 32 480 +WIRE 32 544 -96 544 +WIRE -208 576 -208 544 +FLAG 208 320 0 +FLAG -208 -256 0 +FLAG -208 576 0 +FLAG -496 48 A +IOPIN -496 48 In +FLAG -496 208 B +IOPIN -496 208 In +FLAG 336 128 Y +IOPIN 336 128 Out +SYMBOL nmos -16 256 R0 +SYMATTR InstName M1 +SYMATTR Value N-ENH +SYMBOL nmos -16 384 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL pmos -16 0 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL pmos -16 -128 M180 +SYMATTR InstName M4 +SYMATTR Value P-ENH +SYMBOL .\\positive_threshold_inverter -256 -48 R0 +SYMATTR InstName X1 +SYMBOL .\\positive_threshold_inverter -256 208 R0 +SYMATTR InstName X2 +SYMBOL .\\negative_threshold_inverter -256 -176 R0 +SYMATTR InstName X3 +SYMBOL .\\negative_threshold_inverter -256 336 R0 +SYMATTR InstName X4 +SYMBOL res 16 16 R0 +SYMATTR InstName R1 +SYMATTR Value 100 +SYMBOL res 16 128 R0 +SYMATTR InstName R2 +SYMATTR Value 100 +SYMBOL res 192 176 R0 +SYMATTR InstName R3 +SYMATTR Value 12k +SYMBOL voltage -80 -288 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -80 544 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT -424 -192 Left 0 !.inc ./custom.mos diff --git a/RMOS/gullible.asy b/RMOS/gullible.asy index cd75b7e..7d8ba23 100644 --- a/RMOS/gullible.asy +++ b/RMOS/gullible.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 GUL -SYMATTR Description 2-input gullible gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 GUL +SYMATTR Description 2-input gullible gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/increment.asc b/RMOS/increment.asc index 03d4d5e..af69c4c 100644 --- a/RMOS/increment.asc +++ b/RMOS/increment.asc @@ -1,60 +1,60 @@ -Version 4 -SHEET 1 880 680 -WIRE -192 -192 -224 -192 -WIRE 16 -192 -112 -192 -WIRE -224 -160 -224 -192 -WIRE 16 -128 16 -192 -WIRE -32 -112 -80 -112 -WIRE -80 32 -80 -112 -WIRE -80 32 -192 32 -WIRE 16 32 16 -32 -WIRE 176 32 16 32 -WIRE 304 32 176 32 -WIRE 16 96 16 32 -WIRE 176 96 176 32 -WIRE 16 208 16 176 -WIRE 176 208 176 176 -WIRE -80 288 -80 32 -WIRE -32 288 -80 288 -WIRE 128 288 80 288 -WIRE -192 352 -224 352 -WIRE 176 352 176 304 -WIRE 176 352 -112 352 -WIRE -224 384 -224 352 -FLAG 16 208 0 -FLAG -224 -160 0 -FLAG -224 384 0 -FLAG -192 32 A -IOPIN -192 32 In -FLAG 304 32 Y -IOPIN 304 32 Out -SYMBOL pmos 128 208 R0 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL nmos -32 -32 M180 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL res 0 80 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -96 352 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value 1 -SYMBOL res 160 80 R0 -SYMATTR InstName R2 -SYMATTR Value 100 -SYMBOL voltage -96 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V4 -SYMATTR Value -1 -SYMBOL .\\negative_threshold_inverter 16 240 R0 -SYMATTR InstName X1 -TEXT 160 -96 Left 0 !.inc ./custom.mos -TEXT 72 -176 Left 0 ;Note the switched power rails. +Version 4 +SHEET 1 880 680 +WIRE -192 -192 -224 -192 +WIRE 16 -192 -112 -192 +WIRE -224 -160 -224 -192 +WIRE 16 -128 16 -192 +WIRE -32 -112 -80 -112 +WIRE -80 32 -80 -112 +WIRE -80 32 -192 32 +WIRE 16 32 16 -32 +WIRE 176 32 16 32 +WIRE 304 32 176 32 +WIRE 16 96 16 32 +WIRE 176 96 176 32 +WIRE 16 208 16 176 +WIRE 176 208 176 176 +WIRE -80 288 -80 32 +WIRE -32 288 -80 288 +WIRE 128 288 80 288 +WIRE -192 352 -224 352 +WIRE 176 352 176 304 +WIRE 176 352 -112 352 +WIRE -224 384 -224 352 +FLAG 16 208 0 +FLAG -224 -160 0 +FLAG -224 384 0 +FLAG -192 32 A +IOPIN -192 32 In +FLAG 304 32 Y +IOPIN 304 32 Out +SYMBOL pmos 128 208 R0 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL nmos -32 -32 M180 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL res 0 80 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -96 352 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value 1 +SYMBOL res 160 80 R0 +SYMATTR InstName R2 +SYMATTR Value 100 +SYMBOL voltage -96 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value -1 +SYMBOL .\\negative_threshold_inverter 16 240 R0 +SYMATTR InstName X1 +TEXT 160 -96 Left 0 !.inc ./custom.mos +TEXT 72 -176 Left 0 ;Note the switched power rails. diff --git a/RMOS/increment.asy b/RMOS/increment.asy index b4f6f39..0d06e22 100644 --- a/RMOS/increment.asy +++ b/RMOS/increment.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 +1 -SYMATTR Description Increment gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 +1 +SYMATTR Description Increment gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/inverting_consensus.asc b/RMOS/inverting_consensus.asc index 9f3005f..f0f4b98 100644 --- a/RMOS/inverting_consensus.asc +++ b/RMOS/inverting_consensus.asc @@ -1,67 +1,67 @@ -Version 4 -SHEET 1 880 680 -WIRE -176 -192 -208 -192 -WIRE 48 -192 -96 -192 -WIRE -208 -160 -208 -192 -WIRE 48 -128 48 -192 -WIRE 0 -112 -112 -112 -WIRE 48 0 48 -32 -WIRE 0 16 -48 16 -WIRE -112 48 -112 -112 -WIRE -112 48 -208 48 -WIRE 48 144 48 96 -WIRE 208 144 48 144 -WIRE 368 144 208 144 -WIRE 48 192 48 144 -WIRE 208 192 208 144 -WIRE -48 240 -48 16 -WIRE -48 240 -208 240 -WIRE -48 272 -48 240 -WIRE 0 272 -48 272 -WIRE 48 320 48 288 -WIRE 208 320 208 272 -WIRE -112 400 -112 48 -WIRE 0 400 -112 400 -WIRE -176 480 -208 480 -WIRE 48 480 48 416 -WIRE 48 480 -96 480 -WIRE -208 512 -208 480 -FLAG 208 320 0 -FLAG -208 -160 0 -FLAG -208 512 0 -FLAG -208 48 A -IOPIN -208 48 In -FLAG -208 240 B -IOPIN -208 240 In -FLAG 368 144 Y -IOPIN 368 144 Out -SYMBOL nmos 0 192 R0 -SYMATTR InstName M1 -SYMATTR Value N-ENH -SYMBOL nmos 0 320 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL pmos 0 96 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL pmos 0 -32 M180 -SYMATTR InstName M4 -SYMATTR Value P-ENH -SYMBOL res 192 176 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -80 -192 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -80 480 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT 192 -24 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -176 -192 -208 -192 +WIRE 48 -192 -96 -192 +WIRE -208 -160 -208 -192 +WIRE 48 -128 48 -192 +WIRE 0 -112 -112 -112 +WIRE 48 0 48 -32 +WIRE 0 16 -48 16 +WIRE -112 48 -112 -112 +WIRE -112 48 -208 48 +WIRE 48 144 48 96 +WIRE 208 144 48 144 +WIRE 368 144 208 144 +WIRE 48 192 48 144 +WIRE 208 192 208 144 +WIRE -48 240 -48 16 +WIRE -48 240 -208 240 +WIRE -48 272 -48 240 +WIRE 0 272 -48 272 +WIRE 48 320 48 288 +WIRE 208 320 208 272 +WIRE -112 400 -112 48 +WIRE 0 400 -112 400 +WIRE -176 480 -208 480 +WIRE 48 480 48 416 +WIRE 48 480 -96 480 +WIRE -208 512 -208 480 +FLAG 208 320 0 +FLAG -208 -160 0 +FLAG -208 512 0 +FLAG -208 48 A +IOPIN -208 48 In +FLAG -208 240 B +IOPIN -208 240 In +FLAG 368 144 Y +IOPIN 368 144 Out +SYMBOL nmos 0 192 R0 +SYMATTR InstName M1 +SYMATTR Value N-ENH +SYMBOL nmos 0 320 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL pmos 0 96 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL pmos 0 -32 M180 +SYMATTR InstName M4 +SYMATTR Value P-ENH +SYMBOL res 192 176 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -80 -192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -80 480 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT 192 -24 Left 0 !.inc ./custom.mos diff --git a/RMOS/inverting_consensus.asy b/RMOS/inverting_consensus.asy index c0f87df..54f5aca 100644 --- a/RMOS/inverting_consensus.asy +++ b/RMOS/inverting_consensus.asy @@ -1,23 +1,23 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 56 48 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 0 52 Center 0 CON -SYMATTR Description 2-input inverting consensus -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 CON +SYMATTR Description 2-input inverting consensus +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/is_false.asc b/RMOS/is_false.asc index c222c68..5ec18a0 100644 --- a/RMOS/is_false.asc +++ b/RMOS/is_false.asc @@ -1,43 +1,43 @@ -Version 4 -SHEET 1 880 680 -WIRE -80 -144 -112 -144 -WIRE 128 -144 0 -144 -WIRE -112 -112 -112 -144 -WIRE 128 -96 128 -144 -WIRE 80 -80 32 -80 -WIRE 32 48 32 -80 -WIRE 32 48 -64 48 -WIRE 128 48 128 0 -WIRE 272 48 128 48 -WIRE 128 96 128 48 -WIRE -80 224 -112 224 -WIRE 128 224 128 176 -WIRE 128 224 0 224 -WIRE -112 256 -112 224 -FLAG -112 -112 0 -FLAG -112 256 0 -FLAG -64 48 A -IOPIN -64 48 In -FLAG 272 48 Y -IOPIN 272 48 Out -SYMBOL pmos 80 0 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL res 112 80 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage 16 -144 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage 16 224 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -TEXT 80 288 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -80 -144 -112 -144 +WIRE 128 -144 0 -144 +WIRE -112 -112 -112 -144 +WIRE 128 -96 128 -144 +WIRE 80 -80 32 -80 +WIRE 32 48 32 -80 +WIRE 32 48 -64 48 +WIRE 128 48 128 0 +WIRE 272 48 128 48 +WIRE 128 96 128 48 +WIRE -80 224 -112 224 +WIRE 128 224 128 176 +WIRE 128 224 0 224 +WIRE -112 256 -112 224 +FLAG -112 -112 0 +FLAG -112 256 0 +FLAG -64 48 A +IOPIN -64 48 In +FLAG 272 48 Y +IOPIN 272 48 Out +SYMBOL pmos 80 0 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL res 112 80 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage 16 -144 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage 16 224 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +TEXT 80 288 Left 0 !.inc ./custom.mos diff --git a/RMOS/is_false.asy b/RMOS/is_false.asy index e5e3fee..2204505 100644 --- a/RMOS/is_false.asy +++ b/RMOS/is_false.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 =- -SYMATTR Description IS FALSE gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =- +SYMATTR Description IS FALSE gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/is_true.asc b/RMOS/is_true.asc index cf2546f..77202c9 100644 --- a/RMOS/is_true.asc +++ b/RMOS/is_true.asc @@ -1,12 +1,12 @@ -Version 4 -SHEET 1 880 680 -WIRE 48 160 16 160 -WIRE 304 160 272 160 -FLAG 16 160 A -IOPIN 16 160 In -FLAG 304 160 Y -IOPIN 304 160 Out -SYMBOL .\\positive_threshold_inverter 96 112 R0 -SYMATTR InstName X1 -SYMBOL .\\negative_threshold_inverter 208 112 R0 -SYMATTR InstName X2 +Version 4 +SHEET 1 880 680 +WIRE 48 160 16 160 +WIRE 304 160 272 160 +FLAG 16 160 A +IOPIN 16 160 In +FLAG 304 160 Y +IOPIN 304 160 Out +SYMBOL .\\positive_threshold_inverter 96 112 R0 +SYMATTR InstName X1 +SYMBOL .\\negative_threshold_inverter 208 112 R0 +SYMATTR InstName X2 diff --git a/RMOS/is_true.asy b/RMOS/is_true.asy index 5105d90..0edb8b6 100644 --- a/RMOS/is_true.asy +++ b/RMOS/is_true.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 =+ -SYMATTR Description IS TRUE gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =+ +SYMATTR Description IS TRUE gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/is_unknown.asc b/RMOS/is_unknown.asc index d420750..6565555 100644 --- a/RMOS/is_unknown.asc +++ b/RMOS/is_unknown.asc @@ -1,60 +1,60 @@ -Version 4 -SHEET 1 880 680 -WIRE 112 -176 80 -176 -WIRE 368 -176 192 -176 -WIRE 80 -144 80 -176 -WIRE 368 -128 368 -176 -WIRE 320 -112 240 -112 -WIRE 368 0 368 -32 -WIRE -64 176 -160 176 -WIRE 32 176 -64 176 -WIRE 240 176 240 -112 -WIRE 240 176 144 176 -WIRE 368 176 368 80 -WIRE 544 176 368 176 -WIRE 672 176 544 176 -WIRE 368 272 368 176 -WIRE 544 272 544 176 -WIRE -64 352 -64 176 -WIRE 320 352 -64 352 -WIRE 112 416 80 416 -WIRE 368 416 368 368 -WIRE 368 416 192 416 -WIRE 544 416 544 352 -WIRE 544 416 368 416 -WIRE 80 448 80 416 -FLAG 80 -144 0 -FLAG 80 448 0 -FLAG -160 176 A -IOPIN -160 176 In -FLAG 672 176 Y -IOPIN 672 176 Out -SYMBOL .\\negative_threshold_inverter 80 128 R0 -SYMATTR InstName X1 -SYMBOL pmos 320 -32 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL res 352 -16 R0 -SYMATTR InstName R1 -SYMATTR Value 100 -SYMBOL nmos 320 272 R0 -SYMATTR InstName M2 -SYMATTR Value N-ENH -SYMBOL res 528 256 R0 -SYMATTR InstName R2 -SYMATTR Value 12k -SYMBOL voltage 208 -176 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage 208 416 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT -24 0 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE 112 -176 80 -176 +WIRE 368 -176 192 -176 +WIRE 80 -144 80 -176 +WIRE 368 -128 368 -176 +WIRE 320 -112 240 -112 +WIRE 368 0 368 -32 +WIRE -64 176 -160 176 +WIRE 32 176 -64 176 +WIRE 240 176 240 -112 +WIRE 240 176 144 176 +WIRE 368 176 368 80 +WIRE 544 176 368 176 +WIRE 672 176 544 176 +WIRE 368 272 368 176 +WIRE 544 272 544 176 +WIRE -64 352 -64 176 +WIRE 320 352 -64 352 +WIRE 112 416 80 416 +WIRE 368 416 368 368 +WIRE 368 416 192 416 +WIRE 544 416 544 352 +WIRE 544 416 368 416 +WIRE 80 448 80 416 +FLAG 80 -144 0 +FLAG 80 448 0 +FLAG -160 176 A +IOPIN -160 176 In +FLAG 672 176 Y +IOPIN 672 176 Out +SYMBOL .\\negative_threshold_inverter 80 128 R0 +SYMATTR InstName X1 +SYMBOL pmos 320 -32 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL res 352 -16 R0 +SYMATTR InstName R1 +SYMATTR Value 100 +SYMBOL nmos 320 272 R0 +SYMATTR InstName M2 +SYMATTR Value N-ENH +SYMBOL res 528 256 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +SYMBOL voltage 208 -176 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage 208 416 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT -24 0 Left 0 !.inc ./custom.mos diff --git a/RMOS/is_unknown.asy b/RMOS/is_unknown.asy index 8ffb820..49da4de 100644 --- a/RMOS/is_unknown.asy +++ b/RMOS/is_unknown.asy @@ -1,17 +1,17 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -TEXT 0 48 Center 0 =0 -SYMATTR Description IS UNKNOWN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =0 +SYMATTR Description IS UNKNOWN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/max.asc b/RMOS/max.asc index 5f85c3c..beb9ac9 100644 --- a/RMOS/max.asc +++ b/RMOS/max.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 96 144 64 144 -WIRE 352 160 320 160 -WIRE 96 176 64 176 -FLAG 64 144 A -IOPIN 64 144 In -FLAG 64 176 B -IOPIN 64 176 In -FLAG 352 160 Y -IOPIN 352 160 Out -SYMBOL .\\standard_inverter 256 112 R0 -SYMATTR InstName X2 -SYMBOL .\\antimax 144 96 R0 -SYMATTR InstName X1 +Version 4 +SHEET 1 880 680 +WIRE 96 144 64 144 +WIRE 352 160 320 160 +WIRE 96 176 64 176 +FLAG 64 144 A +IOPIN 64 144 In +FLAG 64 176 B +IOPIN 64 176 In +FLAG 352 160 Y +IOPIN 352 160 Out +SYMBOL .\\standard_inverter 256 112 R0 +SYMATTR InstName X2 +SYMBOL .\\antimax 144 96 R0 +SYMATTR InstName X1 diff --git a/RMOS/max.asy b/RMOS/max.asy index 5552b62..a398f78 100644 --- a/RMOS/max.asy +++ b/RMOS/max.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MAX -SYMATTR Description 2-input MAX gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MAX +SYMATTR Description 2-input MAX gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/min.asc b/RMOS/min.asc index ab97561..653ed0c 100644 --- a/RMOS/min.asc +++ b/RMOS/min.asc @@ -1,15 +1,15 @@ -Version 4 -SHEET 1 880 680 -WIRE 64 144 32 144 -WIRE 320 160 288 160 -WIRE 64 176 32 176 -FLAG 32 144 A -IOPIN 32 144 In -FLAG 32 176 B -IOPIN 32 176 In -FLAG 320 160 Y -IOPIN 320 160 Out -SYMBOL .\\antimin 112 96 R0 -SYMATTR InstName X1 -SYMBOL .\\standard_inverter 224 112 R0 -SYMATTR InstName X2 +Version 4 +SHEET 1 880 680 +WIRE 64 144 32 144 +WIRE 320 160 288 160 +WIRE 64 176 32 176 +FLAG 32 144 A +IOPIN 32 144 In +FLAG 32 176 B +IOPIN 32 176 In +FLAG 320 160 Y +IOPIN 320 160 Out +SYMBOL .\\antimin 112 96 R0 +SYMATTR InstName X1 +SYMBOL .\\standard_inverter 224 112 R0 +SYMATTR InstName X2 diff --git a/RMOS/min.asy b/RMOS/min.asy index 0efa86d..3e5b13c 100644 --- a/RMOS/min.asy +++ b/RMOS/min.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 MIN -SYMATTR Description 2-input MIN gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MIN +SYMATTR Description 2-input MIN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/negative_threshold_inverter.asc b/RMOS/negative_threshold_inverter.asc index c222c68..5ec18a0 100644 --- a/RMOS/negative_threshold_inverter.asc +++ b/RMOS/negative_threshold_inverter.asc @@ -1,43 +1,43 @@ -Version 4 -SHEET 1 880 680 -WIRE -80 -144 -112 -144 -WIRE 128 -144 0 -144 -WIRE -112 -112 -112 -144 -WIRE 128 -96 128 -144 -WIRE 80 -80 32 -80 -WIRE 32 48 32 -80 -WIRE 32 48 -64 48 -WIRE 128 48 128 0 -WIRE 272 48 128 48 -WIRE 128 96 128 48 -WIRE -80 224 -112 224 -WIRE 128 224 128 176 -WIRE 128 224 0 224 -WIRE -112 256 -112 224 -FLAG -112 -112 0 -FLAG -112 256 0 -FLAG -64 48 A -IOPIN -64 48 In -FLAG 272 48 Y -IOPIN 272 48 Out -SYMBOL pmos 80 0 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL res 112 80 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage 16 -144 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage 16 224 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -TEXT 80 288 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -80 -144 -112 -144 +WIRE 128 -144 0 -144 +WIRE -112 -112 -112 -144 +WIRE 128 -96 128 -144 +WIRE 80 -80 32 -80 +WIRE 32 48 32 -80 +WIRE 32 48 -64 48 +WIRE 128 48 128 0 +WIRE 272 48 128 48 +WIRE 128 96 128 48 +WIRE -80 224 -112 224 +WIRE 128 224 128 176 +WIRE 128 224 0 224 +WIRE -112 256 -112 224 +FLAG -112 -112 0 +FLAG -112 256 0 +FLAG -64 48 A +IOPIN -64 48 In +FLAG 272 48 Y +IOPIN 272 48 Out +SYMBOL pmos 80 0 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL res 112 80 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage 16 -144 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage 16 224 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +TEXT 80 288 Left 0 !.inc ./custom.mos diff --git a/RMOS/negative_threshold_inverter.asy b/RMOS/negative_threshold_inverter.asy index 91e3aad..3e4e735 100644 --- a/RMOS/negative_threshold_inverter.asy +++ b/RMOS/negative_threshold_inverter.asy @@ -1,18 +1,18 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -TEXT 0 48 Center 0 NTI -SYMATTR Description Negative threshold inverter -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 NTI +SYMATTR Description Negative threshold inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/positive_threshold_inverter.asc b/RMOS/positive_threshold_inverter.asc index ccd8cef..1c48b48 100644 --- a/RMOS/positive_threshold_inverter.asc +++ b/RMOS/positive_threshold_inverter.asc @@ -1,43 +1,43 @@ -Version 4 -SHEET 1 880 680 -WIRE -96 -48 -128 -48 -WIRE 128 -48 -16 -48 -WIRE -128 -16 -128 -48 -WIRE 128 0 128 -48 -WIRE 32 128 -64 128 -WIRE 128 128 128 80 -WIRE 272 128 128 128 -WIRE 128 192 128 128 -WIRE 32 272 32 128 -WIRE 80 272 32 272 -WIRE -96 336 -128 336 -WIRE 128 336 128 288 -WIRE 128 336 -16 336 -WIRE -128 368 -128 336 -FLAG -128 -16 0 -FLAG -128 368 0 -FLAG -64 128 A -IOPIN -64 128 In -FLAG 272 128 Y -IOPIN 272 128 Out -SYMBOL res 112 -16 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage 0 -48 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage 0 336 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -SYMBOL nmos 80 192 R0 -SYMATTR InstName M1 -SYMATTR Value N-ENH -TEXT 240 -16 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -96 -48 -128 -48 +WIRE 128 -48 -16 -48 +WIRE -128 -16 -128 -48 +WIRE 128 0 128 -48 +WIRE 32 128 -64 128 +WIRE 128 128 128 80 +WIRE 272 128 128 128 +WIRE 128 192 128 128 +WIRE 32 272 32 128 +WIRE 80 272 32 272 +WIRE -96 336 -128 336 +WIRE 128 336 128 288 +WIRE 128 336 -16 336 +WIRE -128 368 -128 336 +FLAG -128 -16 0 +FLAG -128 368 0 +FLAG -64 128 A +IOPIN -64 128 In +FLAG 272 128 Y +IOPIN 272 128 Out +SYMBOL res 112 -16 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage 0 -48 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage 0 336 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +SYMBOL nmos 80 192 R0 +SYMATTR InstName M1 +SYMATTR Value N-ENH +TEXT 240 -16 Left 0 !.inc ./custom.mos diff --git a/RMOS/positive_threshold_inverter.asy b/RMOS/positive_threshold_inverter.asy index 1122cb4..3ce48e9 100644 --- a/RMOS/positive_threshold_inverter.asy +++ b/RMOS/positive_threshold_inverter.asy @@ -1,18 +1,18 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -TEXT 0 48 Center 0 PTI -SYMATTR Description Positive threshold inverter -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 PTI +SYMATTR Description Positive threshold inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/standard_inverter.asc b/RMOS/standard_inverter.asc index 77a4e84..33cb08f 100644 --- a/RMOS/standard_inverter.asc +++ b/RMOS/standard_inverter.asc @@ -1,53 +1,53 @@ -Version 4 -SHEET 1 880 680 -WIRE -288 -160 -320 -160 -WIRE 16 -160 -208 -160 -WIRE -320 -128 -320 -160 -WIRE 16 -112 16 -160 -WIRE -32 -96 -96 -96 -WIRE 16 16 16 -16 -WIRE -96 112 -96 -96 -WIRE -96 112 -208 112 -WIRE 16 112 16 96 -WIRE 176 112 16 112 -WIRE 16 128 16 112 -WIRE 16 240 16 208 -WIRE -96 320 -96 112 -WIRE -32 320 -96 320 -WIRE -288 384 -320 384 -WIRE 16 384 16 336 -WIRE 16 384 -208 384 -WIRE -320 416 -320 384 -FLAG -320 -128 0 -FLAG -320 416 0 -FLAG -208 112 A -IOPIN -208 112 In -FLAG 176 112 Y -IOPIN 176 112 Out -SYMBOL nmos -32 240 R0 -SYMATTR InstName M1 -SYMATTR Value N-ELOW -SYMBOL pmos -32 -16 M180 -SYMATTR InstName M2 -SYMATTR Value P-ELOW -SYMBOL res 0 0 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL res 0 112 R0 -SYMATTR InstName R2 -SYMATTR Value 12k -SYMBOL voltage -192 -160 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -192 384 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V3 -SYMATTR Value -1 -TEXT 152 -152 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -288 -160 -320 -160 +WIRE 16 -160 -208 -160 +WIRE -320 -128 -320 -160 +WIRE 16 -112 16 -160 +WIRE -32 -96 -96 -96 +WIRE 16 16 16 -16 +WIRE -96 112 -96 -96 +WIRE -96 112 -208 112 +WIRE 16 112 16 96 +WIRE 176 112 16 112 +WIRE 16 128 16 112 +WIRE 16 240 16 208 +WIRE -96 320 -96 112 +WIRE -32 320 -96 320 +WIRE -288 384 -320 384 +WIRE 16 384 16 336 +WIRE 16 384 -208 384 +WIRE -320 416 -320 384 +FLAG -320 -128 0 +FLAG -320 416 0 +FLAG -208 112 A +IOPIN -208 112 In +FLAG 176 112 Y +IOPIN 176 112 Out +SYMBOL nmos -32 240 R0 +SYMATTR InstName M1 +SYMATTR Value N-ELOW +SYMBOL pmos -32 -16 M180 +SYMATTR InstName M2 +SYMATTR Value P-ELOW +SYMBOL res 0 0 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL res 0 112 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +SYMBOL voltage -192 -160 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -192 384 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -1 +TEXT 152 -152 Left 0 !.inc ./custom.mos diff --git a/RMOS/standard_inverter.asy b/RMOS/standard_inverter.asy index fe479d7..4a9c820 100644 --- a/RMOS/standard_inverter.asy +++ b/RMOS/standard_inverter.asy @@ -1,18 +1,18 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -TEXT 0 48 Center 0 NEG -SYMATTR Description Inverter -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN 64 48 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 2 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 NEG +SYMATTR Description Inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/sum.asc b/RMOS/sum.asc index e7f90d4..123fdc1 100644 --- a/RMOS/sum.asc +++ b/RMOS/sum.asc @@ -1,194 +1,194 @@ -Version 4 -SHEET 1 880 1044 -WIRE -464 -288 -496 -288 -WIRE -240 -288 -384 -288 -WIRE 16 -288 -240 -288 -WIRE 256 -288 16 -288 -WIRE -496 -256 -496 -288 -WIRE -240 -224 -240 -288 -WIRE 16 -224 16 -288 -WIRE -288 -208 -416 -208 -WIRE -32 -208 -144 -208 -WIRE -864 -64 -928 -64 -WIRE -672 -64 -752 -64 -WIRE -624 -64 -672 -64 -WIRE -144 -64 -144 -208 -WIRE -144 -64 -512 -64 -WIRE -240 -32 -240 -128 -WIRE 16 -32 16 -128 -WIRE 256 -32 256 -288 -WIRE -672 -16 -672 -64 -WIRE -320 -16 -672 -16 -WIRE -288 -16 -320 -16 -WIRE -32 -16 -80 -16 -WIRE 208 -16 112 -16 -WIRE -80 80 -80 -16 -WIRE -80 80 -672 80 -WIRE -928 128 -928 -64 -WIRE -928 128 -1040 128 -WIRE -864 128 -928 128 -WIRE -672 128 -672 80 -WIRE -672 128 -752 128 -WIRE -624 128 -672 128 -WIRE -464 128 -512 128 -WIRE -240 160 -240 64 -WIRE 16 160 16 64 -WIRE 256 160 256 64 -WIRE -288 176 -368 176 -WIRE -32 176 -144 176 -WIRE 208 176 160 176 -WIRE -928 288 -928 128 -WIRE 160 288 160 176 -WIRE 160 288 -928 288 -WIRE -240 336 -240 256 -WIRE 16 336 16 256 -WIRE 16 336 -240 336 -WIRE 256 336 256 256 -WIRE 256 336 16 336 -WIRE 448 336 256 336 -WIRE 576 336 448 336 -WIRE 112 384 112 -16 -WIRE 112 384 -928 384 -WIRE 448 400 448 336 -WIRE -240 416 -240 336 -WIRE 16 416 16 336 -WIRE 256 416 256 336 -WIRE -320 496 -320 -16 -WIRE -288 496 -320 496 -WIRE -80 496 -80 80 -WIRE -32 496 -80 496 -WIRE 160 496 160 288 -WIRE 208 496 160 496 -WIRE 448 528 448 480 -WIRE -928 544 -928 384 -WIRE -928 544 -1040 544 -WIRE -864 544 -928 544 -WIRE -672 544 -752 544 -WIRE -624 544 -672 544 -WIRE -80 544 -512 544 -WIRE -672 592 -672 544 -WIRE -368 592 -368 176 -WIRE -368 592 -672 592 -WIRE -240 608 -240 512 -WIRE 16 608 16 512 -WIRE 256 608 256 512 -WIRE -368 688 -368 592 -WIRE -288 688 -368 688 -WIRE -144 688 -144 176 -WIRE -32 688 -144 688 -WIRE 112 688 112 384 -WIRE 208 688 112 688 -WIRE -928 736 -928 544 -WIRE -864 736 -928 736 -WIRE -672 736 -752 736 -WIRE -624 736 -672 736 -WIRE -416 736 -416 -208 -WIRE -416 736 -512 736 -WIRE -672 784 -672 736 -WIRE -144 784 -144 688 -WIRE -144 784 -672 784 -WIRE -240 800 -240 704 -WIRE 16 800 16 704 -WIRE -464 880 -464 128 -WIRE -288 880 -464 880 -WIRE -80 880 -80 544 -WIRE -32 880 -80 880 -WIRE -464 960 -496 960 -WIRE -240 960 -240 896 -WIRE -240 960 -384 960 -WIRE 16 960 16 896 -WIRE 16 960 -240 960 -WIRE 256 960 256 704 -WIRE 256 960 16 960 -WIRE -496 992 -496 960 -FLAG 448 528 0 -FLAG -496 -256 0 -FLAG -496 992 0 -FLAG -1040 128 A -IOPIN -1040 128 In -FLAG -1040 544 B -IOPIN -1040 544 In -FLAG 576 336 Y -IOPIN 576 336 Out -SYMBOL pmos -288 -128 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos -288 64 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL pmos -288 256 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL pmos -32 256 M180 -SYMATTR InstName M4 -SYMATTR Value P-ENH -SYMBOL pmos -32 64 M180 -SYMATTR InstName M5 -SYMATTR Value P-ENH -SYMBOL pmos -32 -128 M180 -SYMATTR InstName M6 -SYMATTR Value P-ENH -SYMBOL pmos 208 64 M180 -SYMATTR InstName M7 -SYMATTR Value P-ENH -SYMBOL pmos 208 256 M180 -SYMATTR InstName M8 -SYMATTR Value P-ENH -SYMBOL nmos -288 416 R0 -SYMATTR InstName M9 -SYMATTR Value N-ENH -SYMBOL nmos -288 608 R0 -SYMATTR InstName M10 -SYMATTR Value N-ENH -SYMBOL nmos -288 800 R0 -SYMATTR InstName M11 -SYMATTR Value N-ENH -SYMBOL nmos -32 416 R0 -SYMATTR InstName M12 -SYMATTR Value N-ENH -SYMBOL nmos -32 608 R0 -SYMATTR InstName M13 -SYMATTR Value N-ENH -SYMBOL nmos -32 800 R0 -SYMATTR InstName M14 -SYMATTR Value N-ENH -SYMBOL nmos 208 416 R0 -SYMATTR InstName M15 -SYMATTR Value N-ENH -SYMBOL nmos 208 608 R0 -SYMATTR InstName M16 -SYMATTR Value N-ENH -SYMBOL res 432 384 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -368 -288 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -368 960 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -SYMBOL .\\positive_threshold_inverter -576 80 R0 -SYMATTR InstName X1 -SYMBOL .\\positive_threshold_inverter -576 496 R0 -SYMATTR InstName X2 -SYMBOL .\\negative_threshold_inverter -576 688 R0 -SYMATTR InstName X3 -SYMBOL .\\negative_threshold_inverter -576 -112 R0 -SYMATTR InstName X4 -SYMBOL .\\negative_threshold_inverter -816 80 R0 -SYMATTR InstName X5 -SYMBOL .\\negative_threshold_inverter -816 496 R0 -SYMATTR InstName X6 -SYMBOL .\\positive_threshold_inverter -816 688 R0 -SYMATTR InstName X7 -SYMBOL .\\positive_threshold_inverter -816 -112 R0 -SYMATTR InstName X8 -TEXT 384 128 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 1044 +WIRE -464 -288 -496 -288 +WIRE -240 -288 -384 -288 +WIRE 16 -288 -240 -288 +WIRE 256 -288 16 -288 +WIRE -496 -256 -496 -288 +WIRE -240 -224 -240 -288 +WIRE 16 -224 16 -288 +WIRE -288 -208 -416 -208 +WIRE -32 -208 -144 -208 +WIRE -864 -64 -928 -64 +WIRE -672 -64 -752 -64 +WIRE -624 -64 -672 -64 +WIRE -144 -64 -144 -208 +WIRE -144 -64 -512 -64 +WIRE -240 -32 -240 -128 +WIRE 16 -32 16 -128 +WIRE 256 -32 256 -288 +WIRE -672 -16 -672 -64 +WIRE -320 -16 -672 -16 +WIRE -288 -16 -320 -16 +WIRE -32 -16 -80 -16 +WIRE 208 -16 112 -16 +WIRE -80 80 -80 -16 +WIRE -80 80 -672 80 +WIRE -928 128 -928 -64 +WIRE -928 128 -1040 128 +WIRE -864 128 -928 128 +WIRE -672 128 -672 80 +WIRE -672 128 -752 128 +WIRE -624 128 -672 128 +WIRE -464 128 -512 128 +WIRE -240 160 -240 64 +WIRE 16 160 16 64 +WIRE 256 160 256 64 +WIRE -288 176 -368 176 +WIRE -32 176 -144 176 +WIRE 208 176 160 176 +WIRE -928 288 -928 128 +WIRE 160 288 160 176 +WIRE 160 288 -928 288 +WIRE -240 336 -240 256 +WIRE 16 336 16 256 +WIRE 16 336 -240 336 +WIRE 256 336 256 256 +WIRE 256 336 16 336 +WIRE 448 336 256 336 +WIRE 576 336 448 336 +WIRE 112 384 112 -16 +WIRE 112 384 -928 384 +WIRE 448 400 448 336 +WIRE -240 416 -240 336 +WIRE 16 416 16 336 +WIRE 256 416 256 336 +WIRE -320 496 -320 -16 +WIRE -288 496 -320 496 +WIRE -80 496 -80 80 +WIRE -32 496 -80 496 +WIRE 160 496 160 288 +WIRE 208 496 160 496 +WIRE 448 528 448 480 +WIRE -928 544 -928 384 +WIRE -928 544 -1040 544 +WIRE -864 544 -928 544 +WIRE -672 544 -752 544 +WIRE -624 544 -672 544 +WIRE -80 544 -512 544 +WIRE -672 592 -672 544 +WIRE -368 592 -368 176 +WIRE -368 592 -672 592 +WIRE -240 608 -240 512 +WIRE 16 608 16 512 +WIRE 256 608 256 512 +WIRE -368 688 -368 592 +WIRE -288 688 -368 688 +WIRE -144 688 -144 176 +WIRE -32 688 -144 688 +WIRE 112 688 112 384 +WIRE 208 688 112 688 +WIRE -928 736 -928 544 +WIRE -864 736 -928 736 +WIRE -672 736 -752 736 +WIRE -624 736 -672 736 +WIRE -416 736 -416 -208 +WIRE -416 736 -512 736 +WIRE -672 784 -672 736 +WIRE -144 784 -144 688 +WIRE -144 784 -672 784 +WIRE -240 800 -240 704 +WIRE 16 800 16 704 +WIRE -464 880 -464 128 +WIRE -288 880 -464 880 +WIRE -80 880 -80 544 +WIRE -32 880 -80 880 +WIRE -464 960 -496 960 +WIRE -240 960 -240 896 +WIRE -240 960 -384 960 +WIRE 16 960 16 896 +WIRE 16 960 -240 960 +WIRE 256 960 256 704 +WIRE 256 960 16 960 +WIRE -496 992 -496 960 +FLAG 448 528 0 +FLAG -496 -256 0 +FLAG -496 992 0 +FLAG -1040 128 A +IOPIN -1040 128 In +FLAG -1040 544 B +IOPIN -1040 544 In +FLAG 576 336 Y +IOPIN 576 336 Out +SYMBOL pmos -288 -128 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos -288 64 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL pmos -288 256 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL pmos -32 256 M180 +SYMATTR InstName M4 +SYMATTR Value P-ENH +SYMBOL pmos -32 64 M180 +SYMATTR InstName M5 +SYMATTR Value P-ENH +SYMBOL pmos -32 -128 M180 +SYMATTR InstName M6 +SYMATTR Value P-ENH +SYMBOL pmos 208 64 M180 +SYMATTR InstName M7 +SYMATTR Value P-ENH +SYMBOL pmos 208 256 M180 +SYMATTR InstName M8 +SYMATTR Value P-ENH +SYMBOL nmos -288 416 R0 +SYMATTR InstName M9 +SYMATTR Value N-ENH +SYMBOL nmos -288 608 R0 +SYMATTR InstName M10 +SYMATTR Value N-ENH +SYMBOL nmos -288 800 R0 +SYMATTR InstName M11 +SYMATTR Value N-ENH +SYMBOL nmos -32 416 R0 +SYMATTR InstName M12 +SYMATTR Value N-ENH +SYMBOL nmos -32 608 R0 +SYMATTR InstName M13 +SYMATTR Value N-ENH +SYMBOL nmos -32 800 R0 +SYMATTR InstName M14 +SYMATTR Value N-ENH +SYMBOL nmos 208 416 R0 +SYMATTR InstName M15 +SYMATTR Value N-ENH +SYMBOL nmos 208 608 R0 +SYMATTR InstName M16 +SYMATTR Value N-ENH +SYMBOL res 432 384 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -368 -288 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -368 960 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +SYMBOL .\\positive_threshold_inverter -576 80 R0 +SYMATTR InstName X1 +SYMBOL .\\positive_threshold_inverter -576 496 R0 +SYMATTR InstName X2 +SYMBOL .\\negative_threshold_inverter -576 688 R0 +SYMATTR InstName X3 +SYMBOL .\\negative_threshold_inverter -576 -112 R0 +SYMATTR InstName X4 +SYMBOL .\\negative_threshold_inverter -816 80 R0 +SYMATTR InstName X5 +SYMBOL .\\negative_threshold_inverter -816 496 R0 +SYMATTR InstName X6 +SYMBOL .\\positive_threshold_inverter -816 688 R0 +SYMATTR InstName X7 +SYMBOL .\\positive_threshold_inverter -816 -112 R0 +SYMATTR InstName X8 +TEXT 384 128 Left 0 !.inc ./custom.mos diff --git a/RMOS/sum.asy b/RMOS/sum.asy index 3ad5226..4330c6e 100644 --- a/RMOS/sum.asy +++ b/RMOS/sum.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 SUM -SYMATTR Description SUM gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 SUM +SYMATTR Description SUM gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/xor.asc b/RMOS/xor.asc index 954bd7c..c6745cb 100644 --- a/RMOS/xor.asc +++ b/RMOS/xor.asc @@ -1,113 +1,113 @@ -Version 4 -SHEET 1 880 680 -WIRE -256 -272 -288 -272 -WIRE -64 -272 -176 -272 -WIRE 192 -272 -64 -272 -WIRE -288 -240 -288 -272 -WIRE -64 -208 -64 -272 -WIRE 192 -208 192 -272 -WIRE -112 -192 -144 -192 -WIRE 144 -192 96 -192 -WIRE -144 -80 -144 -192 -WIRE -144 -80 -432 -80 -WIRE 48 -80 -144 -80 -WIRE 96 -48 96 -192 -WIRE 96 -48 -240 -48 -WIRE -64 -16 -64 -112 -WIRE 192 -16 192 -112 -WIRE -432 0 -432 -80 -WIRE -432 0 -512 0 -WIRE -384 0 -432 0 -WIRE -240 0 -240 -48 -WIRE -240 0 -272 0 -WIRE -112 0 -192 0 -WIRE 144 0 96 0 -WIRE -240 144 -240 0 -WIRE -144 144 -240 144 -WIRE -64 144 -64 80 -WIRE 192 144 192 80 -WIRE 192 144 -64 144 -WIRE 368 144 192 144 -WIRE 512 144 368 144 -WIRE -64 208 -64 144 -WIRE 192 208 192 144 -WIRE 368 208 368 144 -WIRE -432 288 -512 288 -WIRE -384 288 -432 288 -WIRE -192 288 -192 0 -WIRE -192 288 -272 288 -WIRE -144 288 -144 144 -WIRE -112 288 -144 288 -WIRE 96 288 96 0 -WIRE 144 288 96 288 -WIRE 368 336 368 288 -WIRE -432 352 -432 288 -WIRE 96 352 96 288 -WIRE 96 352 -432 352 -WIRE -64 400 -64 304 -WIRE 192 400 192 304 -WIRE -192 480 -192 288 -WIRE -112 480 -192 480 -WIRE 48 480 48 -80 -WIRE 144 480 48 480 -WIRE -256 560 -288 560 -WIRE -64 560 -64 496 -WIRE -64 560 -176 560 -WIRE 192 560 192 496 -WIRE 192 560 -64 560 -WIRE -288 592 -288 560 -FLAG 368 336 0 -FLAG -288 -240 0 -FLAG -288 592 0 -FLAG -512 0 A -IOPIN -512 0 In -FLAG -512 288 B -IOPIN -512 288 In -FLAG 512 144 Y -IOPIN 512 144 Out -SYMBOL pmos -112 80 M180 -SYMATTR InstName M1 -SYMATTR Value P-ENH -SYMBOL pmos -112 -112 M180 -SYMATTR InstName M2 -SYMATTR Value P-ENH -SYMBOL pmos 144 80 M180 -SYMATTR InstName M3 -SYMATTR Value P-ENH -SYMBOL pmos 144 -112 M180 -SYMATTR InstName M4 -SYMATTR Value P-ENH -SYMBOL nmos -112 208 R0 -SYMATTR InstName M5 -SYMATTR Value N-ENH -SYMBOL nmos -112 400 R0 -SYMATTR InstName M6 -SYMATTR Value N-ENH -SYMBOL nmos 144 208 R0 -SYMATTR InstName M7 -SYMATTR Value N-ENH -SYMBOL nmos 144 400 R0 -SYMATTR InstName M8 -SYMATTR Value N-ENH -SYMBOL .\\standard_inverter -336 -48 R0 -SYMATTR InstName X1 -SYMBOL .\\standard_inverter -336 240 R0 -SYMATTR InstName X2 -SYMBOL res 352 192 R0 -SYMATTR InstName R1 -SYMATTR Value 12k -SYMBOL voltage -160 -272 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V1 -SYMATTR Value 1 -SYMBOL voltage -160 560 R90 -WINDOW 0 -32 56 VBottom 0 -WINDOW 3 32 56 VTop 0 -WINDOW 123 0 0 Left 0 -WINDOW 39 0 0 Left 0 -SYMATTR InstName V2 -SYMATTR Value -1 -TEXT 296 -72 Left 0 !.inc ./custom.mos +Version 4 +SHEET 1 880 680 +WIRE -256 -272 -288 -272 +WIRE -64 -272 -176 -272 +WIRE 192 -272 -64 -272 +WIRE -288 -240 -288 -272 +WIRE -64 -208 -64 -272 +WIRE 192 -208 192 -272 +WIRE -112 -192 -144 -192 +WIRE 144 -192 96 -192 +WIRE -144 -80 -144 -192 +WIRE -144 -80 -432 -80 +WIRE 48 -80 -144 -80 +WIRE 96 -48 96 -192 +WIRE 96 -48 -240 -48 +WIRE -64 -16 -64 -112 +WIRE 192 -16 192 -112 +WIRE -432 0 -432 -80 +WIRE -432 0 -512 0 +WIRE -384 0 -432 0 +WIRE -240 0 -240 -48 +WIRE -240 0 -272 0 +WIRE -112 0 -192 0 +WIRE 144 0 96 0 +WIRE -240 144 -240 0 +WIRE -144 144 -240 144 +WIRE -64 144 -64 80 +WIRE 192 144 192 80 +WIRE 192 144 -64 144 +WIRE 368 144 192 144 +WIRE 512 144 368 144 +WIRE -64 208 -64 144 +WIRE 192 208 192 144 +WIRE 368 208 368 144 +WIRE -432 288 -512 288 +WIRE -384 288 -432 288 +WIRE -192 288 -192 0 +WIRE -192 288 -272 288 +WIRE -144 288 -144 144 +WIRE -112 288 -144 288 +WIRE 96 288 96 0 +WIRE 144 288 96 288 +WIRE 368 336 368 288 +WIRE -432 352 -432 288 +WIRE 96 352 96 288 +WIRE 96 352 -432 352 +WIRE -64 400 -64 304 +WIRE 192 400 192 304 +WIRE -192 480 -192 288 +WIRE -112 480 -192 480 +WIRE 48 480 48 -80 +WIRE 144 480 48 480 +WIRE -256 560 -288 560 +WIRE -64 560 -64 496 +WIRE -64 560 -176 560 +WIRE 192 560 192 496 +WIRE 192 560 -64 560 +WIRE -288 592 -288 560 +FLAG 368 336 0 +FLAG -288 -240 0 +FLAG -288 592 0 +FLAG -512 0 A +IOPIN -512 0 In +FLAG -512 288 B +IOPIN -512 288 In +FLAG 512 144 Y +IOPIN 512 144 Out +SYMBOL pmos -112 80 M180 +SYMATTR InstName M1 +SYMATTR Value P-ENH +SYMBOL pmos -112 -112 M180 +SYMATTR InstName M2 +SYMATTR Value P-ENH +SYMBOL pmos 144 80 M180 +SYMATTR InstName M3 +SYMATTR Value P-ENH +SYMBOL pmos 144 -112 M180 +SYMATTR InstName M4 +SYMATTR Value P-ENH +SYMBOL nmos -112 208 R0 +SYMATTR InstName M5 +SYMATTR Value N-ENH +SYMBOL nmos -112 400 R0 +SYMATTR InstName M6 +SYMATTR Value N-ENH +SYMBOL nmos 144 208 R0 +SYMATTR InstName M7 +SYMATTR Value N-ENH +SYMBOL nmos 144 400 R0 +SYMATTR InstName M8 +SYMATTR Value N-ENH +SYMBOL .\\standard_inverter -336 -48 R0 +SYMATTR InstName X1 +SYMBOL .\\standard_inverter -336 240 R0 +SYMATTR InstName X2 +SYMBOL res 352 192 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL voltage -160 -272 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 1 +SYMBOL voltage -160 560 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value -1 +TEXT 296 -72 Left 0 !.inc ./custom.mos diff --git a/RMOS/xor.asy b/RMOS/xor.asy index bdf30a2..c454326 100644 --- a/RMOS/xor.asy +++ b/RMOS/xor.asy @@ -1,22 +1,22 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -TEXT 1 48 Center 0 XOR -SYMATTR Description XOR gate -PIN -48 48 NONE 0 -PINATTR PinName A -PINATTR SpiceOrder 1 -PIN -48 80 NONE 0 -PINATTR PinName B -PINATTR SpiceOrder 2 -PIN 64 64 NONE 0 -PINATTR PinName Y -PINATTR SpiceOrder 3 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 XOR +SYMATTR Description XOR gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/simulated/2_input_max.asc b/simulated/2_input_max.asc index 52ff328..eb2493d 100644 --- a/simulated/2_input_max.asc +++ b/simulated/2_input_max.asc @@ -1,31 +1,31 @@ -Version 4 -SHEET 1 880 680 -WIRE 144 16 -32 16 -WIRE 320 32 208 32 -WIRE 64 80 -32 80 -WIRE 144 80 96 80 -WIRE 96 144 96 80 -WIRE 96 144 32 144 -WIRE 32 208 32 144 -WIRE 32 208 -32 208 -WIRE 64 208 64 80 -WIRE 144 208 64 208 -WIRE 320 224 208 224 -WIRE 144 272 -32 272 -FLAG -32 16 A- -IOPIN -32 16 In -FLAG -32 80 A+ -IOPIN -32 80 In -FLAG -32 208 B- -IOPIN -32 208 In -FLAG -32 272 B+ -IOPIN -32 272 In -FLAG 320 32 Y- -IOPIN 320 32 Out -FLAG 320 224 Y+ -IOPIN 320 224 Out -SYMBOL Digital\\or 176 176 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 176 -16 R0 -SYMATTR InstName A2 -TEXT 248 312 Left 0 ;Total = 12 transistors +Version 4 +SHEET 1 880 680 +WIRE 144 16 -32 16 +WIRE 320 32 208 32 +WIRE 64 80 -32 80 +WIRE 144 80 96 80 +WIRE 96 144 96 80 +WIRE 96 144 32 144 +WIRE 32 208 32 144 +WIRE 32 208 -32 208 +WIRE 64 208 64 80 +WIRE 144 208 64 208 +WIRE 320 224 208 224 +WIRE 144 272 -32 272 +FLAG -32 16 A- +IOPIN -32 16 In +FLAG -32 80 A+ +IOPIN -32 80 In +FLAG -32 208 B- +IOPIN -32 208 In +FLAG -32 272 B+ +IOPIN -32 272 In +FLAG 320 32 Y- +IOPIN 320 32 Out +FLAG 320 224 Y+ +IOPIN 320 224 Out +SYMBOL Digital\\or 176 176 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 176 -16 R0 +SYMATTR InstName A2 +TEXT 248 312 Left 0 ;Total = 12 transistors diff --git a/simulated/2_input_max.asy b/simulated/2_input_max.asy index f900f55..ddb4786 100644 --- a/simulated/2_input_max.asy +++ b/simulated/2_input_max.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 MAX -SYMATTR Description 2-input MAX gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 MAX +SYMATTR Description 2-input MAX gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/2_input_min.asc b/simulated/2_input_min.asc index 86179cb..37b6577 100644 --- a/simulated/2_input_min.asc +++ b/simulated/2_input_min.asc @@ -1,31 +1,31 @@ -Version 4 -SHEET 1 880 680 -WIRE 144 16 -32 16 -WIRE 320 32 208 32 -WIRE 64 80 -32 80 -WIRE 144 80 96 80 -WIRE 96 144 96 80 -WIRE 96 144 32 144 -WIRE 32 208 32 144 -WIRE 32 208 -32 208 -WIRE 64 208 64 80 -WIRE 144 208 64 208 -WIRE 320 224 208 224 -WIRE 144 272 -32 272 -FLAG -32 16 A- -IOPIN -32 16 In -FLAG -32 80 A+ -IOPIN -32 80 In -FLAG -32 208 B- -IOPIN -32 208 In -FLAG -32 272 B+ -IOPIN -32 272 In -FLAG 320 32 Y- -IOPIN 320 32 Out -FLAG 320 224 Y+ -IOPIN 320 224 Out -SYMBOL Digital\\or 176 -16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 176 176 R0 -SYMATTR InstName A2 -TEXT 248 312 Left 0 ;Total = 12 transistors +Version 4 +SHEET 1 880 680 +WIRE 144 16 -32 16 +WIRE 320 32 208 32 +WIRE 64 80 -32 80 +WIRE 144 80 96 80 +WIRE 96 144 96 80 +WIRE 96 144 32 144 +WIRE 32 208 32 144 +WIRE 32 208 -32 208 +WIRE 64 208 64 80 +WIRE 144 208 64 208 +WIRE 320 224 208 224 +WIRE 144 272 -32 272 +FLAG -32 16 A- +IOPIN -32 16 In +FLAG -32 80 A+ +IOPIN -32 80 In +FLAG -32 208 B- +IOPIN -32 208 In +FLAG -32 272 B+ +IOPIN -32 272 In +FLAG 320 32 Y- +IOPIN 320 32 Out +FLAG 320 224 Y+ +IOPIN 320 224 Out +SYMBOL Digital\\or 176 -16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 176 176 R0 +SYMATTR InstName A2 +TEXT 248 312 Left 0 ;Total = 12 transistors diff --git a/simulated/2_input_min.asy b/simulated/2_input_min.asy index ed919e3..1c442ce 100644 --- a/simulated/2_input_min.asy +++ b/simulated/2_input_min.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 MIN -SYMATTR Description 2-input MIN gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 MIN +SYMATTR Description 2-input MIN gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/buffer.asc b/simulated/buffer.asc index b1a7566..964eacf 100644 --- a/simulated/buffer.asc +++ b/simulated/buffer.asc @@ -1,13 +1,13 @@ -Version 4 -SHEET 1 880 680 -WIRE 288 96 64 96 -WIRE 288 160 64 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 288 96 64 96 +WIRE 288 160 64 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/buffer.asy b/simulated/buffer.asy index de8c658..6527b67 100644 --- a/simulated/buffer.asy +++ b/simulated/buffer.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 BUF -SYMATTR Description Buffer -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 BUF +SYMATTR Description Buffer +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/clamp_down.asc b/simulated/clamp_down.asc index ba95611..6cac961 100644 --- a/simulated/clamp_down.asc +++ b/simulated/clamp_down.asc @@ -1,16 +1,16 @@ -Version 4 -SHEET 1 880 680 -WIRE 288 96 64 96 -WIRE 128 160 64 160 -WIRE 288 160 176 160 -WIRE 176 176 176 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -FLAG 176 176 0 -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 288 96 64 96 +WIRE 128 160 64 160 +WIRE 288 160 176 160 +WIRE 176 176 176 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +FLAG 176 176 0 +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/clamp_down.asy b/simulated/clamp_down.asy index 44deb75..c3fb2fe 100644 --- a/simulated/clamp_down.asy +++ b/simulated/clamp_down.asy @@ -1,33 +1,33 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -64 48 -48 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 64 80 64 64 -LINE Normal 80 80 64 80 -TEXT 1 48 Center 0 MIN -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP DOWN gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN 80 80 NONE 0 -PINATTR PinName Y+ -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 8 -PINATTR PinName Y- -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -64 48 -48 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 64 80 64 64 +LINE Normal 80 80 64 80 +TEXT 1 48 Center 0 MIN +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP DOWN gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN 80 80 NONE 0 +PINATTR PinName Y+ +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 8 +PINATTR PinName Y- +PINATTR SpiceOrder 4 diff --git a/simulated/clamp_up.asc b/simulated/clamp_up.asc index e260cad..59563e5 100644 --- a/simulated/clamp_up.asc +++ b/simulated/clamp_up.asc @@ -1,16 +1,16 @@ -Version 4 -SHEET 1 880 680 -WIRE 128 96 64 96 -WIRE 288 96 176 96 -WIRE 176 112 176 96 -WIRE 288 160 64 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -FLAG 176 112 0 -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 128 96 64 96 +WIRE 288 96 176 96 +WIRE 176 112 176 96 +WIRE 288 160 64 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +FLAG 176 112 0 +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/clamp_up.asy b/simulated/clamp_up.asy index 26415b5..c5ed36e 100644 --- a/simulated/clamp_up.asy +++ b/simulated/clamp_up.asy @@ -1,33 +1,33 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -64 48 -48 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 64 80 64 64 -LINE Normal 80 80 64 80 -TEXT 1 48 Center 0 MAX -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP UP gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN 80 80 NONE 0 -PINATTR PinName Y+ -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 8 -PINATTR PinName Y- -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -64 48 -48 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 64 80 64 64 +LINE Normal 80 80 64 80 +TEXT 1 48 Center 0 MAX +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP UP gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN 80 80 NONE 0 +PINATTR PinName Y+ +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 8 +PINATTR PinName Y- +PINATTR SpiceOrder 4 diff --git a/simulated/consensus.asc b/simulated/consensus.asc index 6569a51..5b41ef4 100644 --- a/simulated/consensus.asc +++ b/simulated/consensus.asc @@ -1,31 +1,31 @@ -Version 4 -SHEET 1 880 680 -WIRE 144 16 -32 16 -WIRE 320 32 208 32 -WIRE 64 80 -32 80 -WIRE 144 80 96 80 -WIRE 96 144 96 80 -WIRE 96 144 32 144 -WIRE 32 208 32 144 -WIRE 32 208 -32 208 -WIRE 64 208 64 80 -WIRE 144 208 64 208 -WIRE 320 224 208 224 -WIRE 144 272 -32 272 -FLAG -32 16 A- -IOPIN -32 16 In -FLAG -32 80 A+ -IOPIN -32 80 In -FLAG -32 208 B- -IOPIN -32 208 In -FLAG -32 272 B+ -IOPIN -32 272 In -FLAG 320 32 Y- -IOPIN 320 32 Out -FLAG 320 224 Y+ -IOPIN 320 224 Out -SYMBOL Digital\\and 176 176 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 176 -16 R0 -SYMATTR InstName A1 -TEXT 248 312 Left 0 ;Total = 12 transistors +Version 4 +SHEET 1 880 680 +WIRE 144 16 -32 16 +WIRE 320 32 208 32 +WIRE 64 80 -32 80 +WIRE 144 80 96 80 +WIRE 96 144 96 80 +WIRE 96 144 32 144 +WIRE 32 208 32 144 +WIRE 32 208 -32 208 +WIRE 64 208 64 80 +WIRE 144 208 64 208 +WIRE 320 224 208 224 +WIRE 144 272 -32 272 +FLAG -32 16 A- +IOPIN -32 16 In +FLAG -32 80 A+ +IOPIN -32 80 In +FLAG -32 208 B- +IOPIN -32 208 In +FLAG -32 272 B+ +IOPIN -32 272 In +FLAG 320 32 Y- +IOPIN 320 32 Out +FLAG 320 224 Y+ +IOPIN 320 224 Out +SYMBOL Digital\\and 176 176 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 176 -16 R0 +SYMATTR InstName A1 +TEXT 248 312 Left 0 ;Total = 12 transistors diff --git a/simulated/consensus.asy b/simulated/consensus.asy index 03c6620..1b7a24d 100644 --- a/simulated/consensus.asy +++ b/simulated/consensus.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 CON -SYMATTR Description 2-input consensus gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 CON +SYMATTR Description 2-input consensus gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/decrement.asc b/simulated/decrement.asc index cb2d762..9f3c06b 100644 --- a/simulated/decrement.asc +++ b/simulated/decrement.asc @@ -1,27 +1,27 @@ -Version 4 -SHEET 1 880 680 -WIRE 112 48 -128 48 -WIRE 240 96 176 96 -WIRE 320 96 240 96 -WIRE 112 112 -48 112 -WIRE 240 176 240 96 -WIRE 240 176 64 176 -WIRE 64 224 64 176 -WIRE 112 224 64 224 -WIRE 320 272 176 272 -WIRE -48 288 -48 112 -WIRE -48 288 -128 288 -WIRE 112 288 -48 288 -FLAG -128 48 A- -IOPIN -128 48 In -FLAG -128 288 A+ -IOPIN -128 288 In -FLAG 320 96 Y- -IOPIN 320 96 Out -FLAG 320 272 Y+ -IOPIN 320 272 Out -SYMBOL Digital\\or 144 16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 144 192 R0 -SYMATTR InstName A2 -TEXT 168 344 Left 0 ;Total = 8 transistors +Version 4 +SHEET 1 880 680 +WIRE 112 48 -128 48 +WIRE 240 96 176 96 +WIRE 320 96 240 96 +WIRE 112 112 -48 112 +WIRE 240 176 240 96 +WIRE 240 176 64 176 +WIRE 64 224 64 176 +WIRE 112 224 64 224 +WIRE 320 272 176 272 +WIRE -48 288 -48 112 +WIRE -48 288 -128 288 +WIRE 112 288 -48 288 +FLAG -128 48 A- +IOPIN -128 48 In +FLAG -128 288 A+ +IOPIN -128 288 In +FLAG 320 96 Y- +IOPIN 320 96 Out +FLAG 320 272 Y+ +IOPIN 320 272 Out +SYMBOL Digital\\or 144 16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 144 192 R0 +SYMATTR InstName A2 +TEXT 168 344 Left 0 ;Total = 8 transistors diff --git a/simulated/decrement.asy b/simulated/decrement.asy index 7405a55..a8b80f8 100644 --- a/simulated/decrement.asy +++ b/simulated/decrement.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 -1 -SYMATTR Description DECREMENT gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 -1 +SYMATTR Description DECREMENT gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/equality.asc b/simulated/equality.asc index cf3927e..4c3e0a0 100644 --- a/simulated/equality.asc +++ b/simulated/equality.asc @@ -1,51 +1,51 @@ -Version 4 -SHEET 1 880 680 -WIRE -112 -16 -160 -16 -WIRE 32 -16 -112 -16 -WIRE 160 32 96 32 -WIRE -48 48 -160 48 -WIRE 32 48 -16 48 -WIRE -48 128 -48 48 -WIRE 32 128 -48 128 -WIRE 160 128 160 32 -WIRE 224 128 160 128 -WIRE 368 144 288 144 -WIRE 224 160 144 160 -WIRE 144 176 144 160 -WIRE 144 176 96 176 -WIRE 368 176 288 176 -WIRE 32 192 -80 192 -WIRE 224 192 160 192 -WIRE -16 272 -16 48 -WIRE -16 272 -160 272 -WIRE 32 272 -16 272 -WIRE -112 288 -112 -16 -WIRE 32 288 -112 288 -WIRE 160 288 160 192 -WIRE 160 288 96 288 -WIRE -48 320 -48 128 -WIRE 32 320 -48 320 -WIRE -80 336 -80 192 -WIRE -80 336 -160 336 -WIRE 32 336 -80 336 -FLAG 368 144 Y- -IOPIN 368 144 Out -FLAG 368 176 Y+ -IOPIN 368 176 Out -FLAG -160 -16 A- -IOPIN -160 -16 In -FLAG -160 48 A+ -IOPIN -160 48 In -FLAG -160 272 B- -IOPIN -160 272 In -FLAG -160 336 B+ -IOPIN -160 336 In -SYMBOL Digital\\and 256 96 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 64 96 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 64 -48 R0 -SYMATTR InstName A3 -SYMBOL Digital\\or 64 240 R0 -SYMATTR InstName A4 -TEXT 224 272 Left 0 ;Total = 26 transistors +Version 4 +SHEET 1 880 680 +WIRE -112 -16 -160 -16 +WIRE 32 -16 -112 -16 +WIRE 160 32 96 32 +WIRE -48 48 -160 48 +WIRE 32 48 -16 48 +WIRE -48 128 -48 48 +WIRE 32 128 -48 128 +WIRE 160 128 160 32 +WIRE 224 128 160 128 +WIRE 368 144 288 144 +WIRE 224 160 144 160 +WIRE 144 176 144 160 +WIRE 144 176 96 176 +WIRE 368 176 288 176 +WIRE 32 192 -80 192 +WIRE 224 192 160 192 +WIRE -16 272 -16 48 +WIRE -16 272 -160 272 +WIRE 32 272 -16 272 +WIRE -112 288 -112 -16 +WIRE 32 288 -112 288 +WIRE 160 288 160 192 +WIRE 160 288 96 288 +WIRE -48 320 -48 128 +WIRE 32 320 -48 320 +WIRE -80 336 -80 192 +WIRE -80 336 -160 336 +WIRE 32 336 -80 336 +FLAG 368 144 Y- +IOPIN 368 144 Out +FLAG 368 176 Y+ +IOPIN 368 176 Out +FLAG -160 -16 A- +IOPIN -160 -16 In +FLAG -160 48 A+ +IOPIN -160 48 In +FLAG -160 272 B- +IOPIN -160 272 In +FLAG -160 336 B+ +IOPIN -160 336 In +SYMBOL Digital\\and 256 96 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 64 96 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 64 -48 R0 +SYMATTR InstName A3 +SYMBOL Digital\\or 64 240 R0 +SYMATTR InstName A4 +TEXT 224 272 Left 0 ;Total = 26 transistors diff --git a/simulated/equality.asy b/simulated/equality.asy index 1c81763..8f852e1 100644 --- a/simulated/equality.asy +++ b/simulated/equality.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 = -SYMATTR Description 2-input equality gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 = +SYMATTR Description 2-input equality gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/gullible.asc b/simulated/gullible.asc index 0589e69..8e0a2bd 100644 --- a/simulated/gullible.asc +++ b/simulated/gullible.asc @@ -1,43 +1,43 @@ -Version 4 -SHEET 1 880 680 -WIRE 64 48 -96 48 -WIRE 192 64 128 64 -WIRE 224 96 128 96 -WIRE 368 96 288 96 -WIRE -48 112 -96 112 -WIRE 64 112 -16 112 -WIRE 224 112 160 112 -WIRE -48 176 -48 112 -WIRE 16 176 -48 176 -WIRE -16 240 -16 112 -WIRE -16 240 -96 240 -WIRE 16 240 16 176 -WIRE 64 240 16 240 -WIRE 192 240 192 64 -WIRE 224 240 192 240 -WIRE 160 256 160 112 -WIRE 160 256 128 256 -WIRE 224 288 128 288 -WIRE 368 288 288 288 -WIRE 64 304 -96 304 -FLAG -96 112 A+ -IOPIN -96 112 In -FLAG -96 48 A- -IOPIN -96 48 In -FLAG -96 240 B- -IOPIN -96 240 In -FLAG -96 304 B+ -IOPIN -96 304 In -FLAG 368 96 Y- -IOPIN 368 96 Out -FLAG 368 288 Y+ -IOPIN 368 288 Out -SYMBOL Digital\\or 96 16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 96 208 R0 -SYMATTR InstName A2 -SYMBOL Digital\\or 256 16 R0 -SYMATTR InstName A3 -SYMBOL Digital\\or 256 208 R0 -SYMATTR InstName A4 -TEXT 232 384 Left 0 ;Total = 20 transistors +Version 4 +SHEET 1 880 680 +WIRE 64 48 -96 48 +WIRE 192 64 128 64 +WIRE 224 96 128 96 +WIRE 368 96 288 96 +WIRE -48 112 -96 112 +WIRE 64 112 -16 112 +WIRE 224 112 160 112 +WIRE -48 176 -48 112 +WIRE 16 176 -48 176 +WIRE -16 240 -16 112 +WIRE -16 240 -96 240 +WIRE 16 240 16 176 +WIRE 64 240 16 240 +WIRE 192 240 192 64 +WIRE 224 240 192 240 +WIRE 160 256 160 112 +WIRE 160 256 128 256 +WIRE 224 288 128 288 +WIRE 368 288 288 288 +WIRE 64 304 -96 304 +FLAG -96 112 A+ +IOPIN -96 112 In +FLAG -96 48 A- +IOPIN -96 48 In +FLAG -96 240 B- +IOPIN -96 240 In +FLAG -96 304 B+ +IOPIN -96 304 In +FLAG 368 96 Y- +IOPIN 368 96 Out +FLAG 368 288 Y+ +IOPIN 368 288 Out +SYMBOL Digital\\or 96 16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 96 208 R0 +SYMATTR InstName A2 +SYMBOL Digital\\or 256 16 R0 +SYMATTR InstName A3 +SYMBOL Digital\\or 256 208 R0 +SYMATTR InstName A4 +TEXT 232 384 Left 0 ;Total = 20 transistors diff --git a/simulated/gullible.asy b/simulated/gullible.asy index d7cf229..5bb7f99 100644 --- a/simulated/gullible.asy +++ b/simulated/gullible.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 GUL -SYMATTR Description 2-input gullible gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 GUL +SYMATTR Description 2-input gullible gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/increment.asc b/simulated/increment.asc index f2f5fcb..f387838 100644 --- a/simulated/increment.asc +++ b/simulated/increment.asc @@ -1,27 +1,27 @@ -Version 4 -SHEET 1 880 680 -WIRE -48 48 -128 48 -WIRE 112 48 -48 48 -WIRE 320 96 176 96 -WIRE 112 112 64 112 -WIRE 64 176 64 112 -WIRE 240 176 64 176 -WIRE -48 224 -48 48 -WIRE 112 224 -48 224 -WIRE 240 272 240 176 -WIRE 240 272 176 272 -WIRE 320 272 240 272 -WIRE 112 288 -128 288 -FLAG -128 48 A- -IOPIN -128 48 In -FLAG -128 288 A+ -IOPIN -128 288 In -FLAG 320 96 Y- -IOPIN 320 96 Out -FLAG 320 272 Y+ -IOPIN 320 272 Out -SYMBOL Digital\\or 144 16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 144 192 R0 -SYMATTR InstName A2 -TEXT 168 344 Left 0 ;Total = 8 transistors +Version 4 +SHEET 1 880 680 +WIRE -48 48 -128 48 +WIRE 112 48 -48 48 +WIRE 320 96 176 96 +WIRE 112 112 64 112 +WIRE 64 176 64 112 +WIRE 240 176 64 176 +WIRE -48 224 -48 48 +WIRE 112 224 -48 224 +WIRE 240 272 240 176 +WIRE 240 272 176 272 +WIRE 320 272 240 272 +WIRE 112 288 -128 288 +FLAG -128 48 A- +IOPIN -128 48 In +FLAG -128 288 A+ +IOPIN -128 288 In +FLAG 320 96 Y- +IOPIN 320 96 Out +FLAG 320 272 Y+ +IOPIN 320 272 Out +SYMBOL Digital\\or 144 16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 144 192 R0 +SYMATTR InstName A2 +TEXT 168 344 Left 0 ;Total = 8 transistors diff --git a/simulated/increment.asy b/simulated/increment.asy index bb089d8..41cc792 100644 --- a/simulated/increment.asy +++ b/simulated/increment.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 +1 -SYMATTR Description INCREMENT gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 +1 +SYMATTR Description INCREMENT gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/is_false.asc b/simulated/is_false.asc index 8d7d1d6..bfb6e2e 100644 --- a/simulated/is_false.asc +++ b/simulated/is_false.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 32 64 -48 64 -WIRE 96 64 32 64 -WIRE 240 64 160 64 -WIRE 0 128 -48 128 -WIRE 32 128 32 64 -WIRE 240 128 32 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 0 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 32 64 -48 64 +WIRE 96 64 32 64 +WIRE 240 64 160 64 +WIRE 0 128 -48 128 +WIRE 32 128 32 64 +WIRE 240 128 32 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 0 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/is_false.asy b/simulated/is_false.asy index e0ff789..2f21c93 100644 --- a/simulated/is_false.asy +++ b/simulated/is_false.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 =- -SYMATTR Description IS FALSE gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 =- +SYMATTR Description IS FALSE gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/is_true.asc b/simulated/is_true.asc index 0839114..7a133be 100644 --- a/simulated/is_true.asc +++ b/simulated/is_true.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 0 64 -48 64 -WIRE 96 64 32 64 -WIRE 240 64 160 64 -WIRE 32 128 32 64 -WIRE 32 128 -48 128 -WIRE 240 128 32 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 0 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 0 64 -48 64 +WIRE 96 64 32 64 +WIRE 240 64 160 64 +WIRE 32 128 32 64 +WIRE 32 128 -48 128 +WIRE 240 128 32 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 0 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/is_true.asy b/simulated/is_true.asy index aced3f6..cddae6b 100644 --- a/simulated/is_true.asy +++ b/simulated/is_true.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 =+ -SYMATTR Description IS TRUE gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 =+ +SYMATTR Description IS TRUE gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/is_unknown.asc b/simulated/is_unknown.asc index bc40aa2..e33ac33 100644 --- a/simulated/is_unknown.asc +++ b/simulated/is_unknown.asc @@ -1,17 +1,17 @@ -Version 4 -SHEET 1 880 680 -WIRE 64 64 -48 64 -WIRE 240 80 128 80 -WIRE 240 112 128 112 -WIRE 64 128 -48 128 -FLAG 240 80 Y- -IOPIN 240 80 Out -FLAG 240 112 Y+ -IOPIN 240 112 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\or 96 32 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 6 transistors +Version 4 +SHEET 1 880 680 +WIRE 64 64 -48 64 +WIRE 240 80 128 80 +WIRE 240 112 128 112 +WIRE 64 128 -48 128 +FLAG 240 80 Y- +IOPIN 240 80 Out +FLAG 240 112 Y+ +IOPIN 240 112 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\or 96 32 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 6 transistors diff --git a/simulated/is_unknown.asy b/simulated/is_unknown.asy index 40fc34a..a838309 100644 --- a/simulated/is_unknown.asy +++ b/simulated/is_unknown.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 =0 -SYMATTR Description IS UNKNOWN gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 =0 +SYMATTR Description IS UNKNOWN gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/negative_threshold_inverter.asc b/simulated/negative_threshold_inverter.asc index 8d7d1d6..bfb6e2e 100644 --- a/simulated/negative_threshold_inverter.asc +++ b/simulated/negative_threshold_inverter.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 32 64 -48 64 -WIRE 96 64 32 64 -WIRE 240 64 160 64 -WIRE 0 128 -48 128 -WIRE 32 128 32 64 -WIRE 240 128 32 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 0 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 32 64 -48 64 +WIRE 96 64 32 64 +WIRE 240 64 160 64 +WIRE 0 128 -48 128 +WIRE 32 128 32 64 +WIRE 240 128 32 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 0 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/negative_threshold_inverter.asy b/simulated/negative_threshold_inverter.asy index 88aa7bd..8e0c1f5 100644 --- a/simulated/negative_threshold_inverter.asy +++ b/simulated/negative_threshold_inverter.asy @@ -1,32 +1,32 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 NTI -SYMATTR Description Negative threshold inverter -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 NTI +SYMATTR Description Negative threshold inverter +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/positive_threshold_inverter.asc b/simulated/positive_threshold_inverter.asc index 983226c..4daed9d 100644 --- a/simulated/positive_threshold_inverter.asc +++ b/simulated/positive_threshold_inverter.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 0 64 -48 64 -WIRE 240 64 32 64 -WIRE 32 128 32 64 -WIRE 32 128 -48 128 -WIRE 96 128 32 128 -WIRE 240 128 160 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 64 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 0 64 -48 64 +WIRE 240 64 32 64 +WIRE 32 128 32 64 +WIRE 32 128 -48 128 +WIRE 96 128 32 128 +WIRE 240 128 160 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 64 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/positive_threshold_inverter.asy b/simulated/positive_threshold_inverter.asy index a180db8..9eeb9e2 100644 --- a/simulated/positive_threshold_inverter.asy +++ b/simulated/positive_threshold_inverter.asy @@ -1,32 +1,32 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 PTI -SYMATTR Description Positive threshold inverter -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 PTI +SYMATTR Description Positive threshold inverter +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/standard_inverter.asc b/simulated/standard_inverter.asc index a0a58b0..8c4f4a5 100644 --- a/simulated/standard_inverter.asc +++ b/simulated/standard_inverter.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 176 96 64 96 -WIRE 288 96 208 96 -WIRE 208 128 208 96 -WIRE 208 128 144 128 -WIRE 144 160 144 128 -WIRE 144 160 64 160 -WIRE 176 160 176 96 -WIRE 288 160 176 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 176 96 64 96 +WIRE 288 96 208 96 +WIRE 208 128 208 96 +WIRE 208 128 144 128 +WIRE 144 160 144 128 +WIRE 144 160 64 160 +WIRE 176 160 176 96 +WIRE 288 160 176 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/standard_inverter.asy b/simulated/standard_inverter.asy index 4a10402..d43138c 100644 --- a/simulated/standard_inverter.asy +++ b/simulated/standard_inverter.asy @@ -1,32 +1,32 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 NEG -SYMATTR Description Inverter -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 NEG +SYMATTR Description Inverter +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/sum.asc b/simulated/sum.asc index 8edf7a5..7d520c3 100644 --- a/simulated/sum.asc +++ b/simulated/sum.asc @@ -1,94 +1,94 @@ -Version 4 -SHEET 1 880 680 -WIRE 160 -224 -176 -224 -WIRE 320 -176 224 -176 -WIRE 160 -160 -144 -160 -WIRE 160 -96 -112 -96 -WIRE 112 -64 -80 -64 -WIRE 288 -48 224 -48 -WIRE 160 -32 80 -32 -WIRE -112 32 -112 -96 -WIRE -112 32 -256 32 -WIRE -32 32 -112 32 -WIRE 112 32 112 -64 -WIRE 160 32 112 32 -WIRE 320 32 320 -176 -WIRE 352 32 320 32 -WIRE 288 64 288 -48 -WIRE 352 64 288 64 -WIRE 112 80 32 80 -WIRE 256 80 224 80 -WIRE 528 80 416 80 -WIRE -144 96 -144 -160 -WIRE -144 96 -256 96 -WIRE -32 96 -144 96 -WIRE 112 96 112 80 -WIRE 160 96 112 96 -WIRE 256 96 256 80 -WIRE 352 96 256 96 -WIRE -80 176 -80 -64 -WIRE -80 176 -256 176 -WIRE -32 176 -80 176 -WIRE 112 176 112 96 -WIRE 160 176 112 176 -WIRE 352 176 256 176 -WIRE 352 208 288 208 -WIRE 80 224 80 -32 -WIRE 80 224 32 224 -WIRE 256 224 256 176 -WIRE 256 224 224 224 -WIRE 528 224 416 224 -WIRE -208 240 -256 240 -WIRE -176 240 -176 -224 -WIRE -176 240 -208 240 -WIRE -32 240 -176 240 -WIRE 160 240 112 240 -WIRE 352 240 320 240 -WIRE 80 304 80 224 -WIRE 160 304 80 304 -WIRE -208 336 -208 240 -WIRE 112 336 112 240 -WIRE 112 336 -208 336 -WIRE 288 352 288 208 -WIRE 288 352 224 352 -WIRE -144 368 -144 96 -WIRE 160 368 -144 368 -WIRE -112 432 -112 32 -WIRE 160 432 -112 432 -WIRE 320 480 320 240 -WIRE 320 480 224 480 -WIRE -80 496 -80 176 -WIRE 160 496 -80 496 -FLAG 528 80 Y- -IOPIN 528 80 Out -FLAG 528 224 Y+ -IOPIN 528 224 Out -FLAG -256 32 A- -IOPIN -256 32 In -FLAG -256 96 A+ -IOPIN -256 96 In -FLAG -256 176 B- -IOPIN -256 176 In -FLAG -256 240 B+ -IOPIN -256 240 In -SYMBOL Digital\\or 0 0 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 0 144 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 192 0 R0 -SYMATTR InstName A3 -SYMBOL Digital\\and 192 144 R0 -SYMATTR InstName A4 -SYMBOL Digital\\and 192 -128 R0 -SYMATTR InstName A5 -SYMBOL Digital\\and 192 -256 R0 -SYMATTR InstName A6 -SYMBOL Digital\\and 192 272 R0 -SYMATTR InstName A7 -SYMBOL Digital\\and 192 400 R0 -SYMATTR InstName A8 -SYMBOL Digital\\and 384 144 R0 -SYMATTR InstName A9 -SYMBOL Digital\\and 384 0 R0 -SYMATTR InstName A10 -TEXT 408 328 Left 0 ;Total = 44 transistors +Version 4 +SHEET 1 880 680 +WIRE 160 -224 -176 -224 +WIRE 320 -176 224 -176 +WIRE 160 -160 -144 -160 +WIRE 160 -96 -112 -96 +WIRE 112 -64 -80 -64 +WIRE 288 -48 224 -48 +WIRE 160 -32 80 -32 +WIRE -112 32 -112 -96 +WIRE -112 32 -256 32 +WIRE -32 32 -112 32 +WIRE 112 32 112 -64 +WIRE 160 32 112 32 +WIRE 320 32 320 -176 +WIRE 352 32 320 32 +WIRE 288 64 288 -48 +WIRE 352 64 288 64 +WIRE 112 80 32 80 +WIRE 256 80 224 80 +WIRE 528 80 416 80 +WIRE -144 96 -144 -160 +WIRE -144 96 -256 96 +WIRE -32 96 -144 96 +WIRE 112 96 112 80 +WIRE 160 96 112 96 +WIRE 256 96 256 80 +WIRE 352 96 256 96 +WIRE -80 176 -80 -64 +WIRE -80 176 -256 176 +WIRE -32 176 -80 176 +WIRE 112 176 112 96 +WIRE 160 176 112 176 +WIRE 352 176 256 176 +WIRE 352 208 288 208 +WIRE 80 224 80 -32 +WIRE 80 224 32 224 +WIRE 256 224 256 176 +WIRE 256 224 224 224 +WIRE 528 224 416 224 +WIRE -208 240 -256 240 +WIRE -176 240 -176 -224 +WIRE -176 240 -208 240 +WIRE -32 240 -176 240 +WIRE 160 240 112 240 +WIRE 352 240 320 240 +WIRE 80 304 80 224 +WIRE 160 304 80 304 +WIRE -208 336 -208 240 +WIRE 112 336 112 240 +WIRE 112 336 -208 336 +WIRE 288 352 288 208 +WIRE 288 352 224 352 +WIRE -144 368 -144 96 +WIRE 160 368 -144 368 +WIRE -112 432 -112 32 +WIRE 160 432 -112 432 +WIRE 320 480 320 240 +WIRE 320 480 224 480 +WIRE -80 496 -80 176 +WIRE 160 496 -80 496 +FLAG 528 80 Y- +IOPIN 528 80 Out +FLAG 528 224 Y+ +IOPIN 528 224 Out +FLAG -256 32 A- +IOPIN -256 32 In +FLAG -256 96 A+ +IOPIN -256 96 In +FLAG -256 176 B- +IOPIN -256 176 In +FLAG -256 240 B+ +IOPIN -256 240 In +SYMBOL Digital\\or 0 0 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 0 144 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 192 0 R0 +SYMATTR InstName A3 +SYMBOL Digital\\and 192 144 R0 +SYMATTR InstName A4 +SYMBOL Digital\\and 192 -128 R0 +SYMATTR InstName A5 +SYMBOL Digital\\and 192 -256 R0 +SYMATTR InstName A6 +SYMBOL Digital\\and 192 272 R0 +SYMATTR InstName A7 +SYMBOL Digital\\and 192 400 R0 +SYMATTR InstName A8 +SYMBOL Digital\\and 384 144 R0 +SYMATTR InstName A9 +SYMBOL Digital\\and 384 0 R0 +SYMATTR InstName A10 +TEXT 408 328 Left 0 ;Total = 44 transistors diff --git a/simulated/sum.asy b/simulated/sum.asy index f72c0e1..c9e9227 100644 --- a/simulated/sum.asy +++ b/simulated/sum.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 SUM -SYMATTR Description SUM gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 SUM +SYMATTR Description SUM gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/xor.asc b/simulated/xor.asc index fdc5ed7..16ebdc7 100644 --- a/simulated/xor.asc +++ b/simulated/xor.asc @@ -1,59 +1,59 @@ -Version 4 -SHEET 1 880 680 -WIRE -96 -32 -192 -32 -WIRE 48 -32 -96 -32 -WIRE 160 16 112 16 -WIRE -32 32 -192 32 -WIRE 48 32 0 32 -WIRE 160 48 160 16 -WIRE 224 48 160 48 -WIRE 224 80 160 80 -WIRE 384 80 288 80 -WIRE -32 96 -32 32 -WIRE 48 96 -32 96 -WIRE 160 144 160 80 -WIRE 160 144 112 144 -WIRE 48 160 -64 160 -WIRE -96 224 -96 -32 -WIRE 48 224 -96 224 -WIRE 160 272 112 272 -WIRE -64 288 -64 160 -WIRE 48 288 -64 288 -WIRE 160 304 160 272 -WIRE 224 304 160 304 -WIRE 224 336 160 336 -WIRE 384 336 288 336 -WIRE 0 352 0 32 -WIRE 0 352 -192 352 -WIRE 48 352 0 352 -WIRE 160 400 160 336 -WIRE 160 400 112 400 -WIRE -64 416 -64 288 -WIRE -64 416 -192 416 -WIRE -32 416 -32 96 -WIRE 48 416 -32 416 -FLAG 384 80 Y- -IOPIN 384 80 Out -FLAG 384 336 Y+ -IOPIN 384 336 Out -FLAG -192 -32 A- -IOPIN -192 -32 In -FLAG -192 32 A+ -IOPIN -192 32 In -FLAG -192 352 B- -IOPIN -192 352 In -FLAG -192 416 B+ -IOPIN -192 416 In -SYMBOL Digital\\and 80 -64 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 80 64 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 80 192 R0 -SYMATTR InstName A3 -SYMBOL Digital\\and 80 320 R0 -SYMATTR InstName A4 -SYMBOL Digital\\and 256 256 R0 -SYMATTR InstName A5 -SYMBOL Digital\\and 256 0 R0 -SYMATTR InstName A6 -TEXT 216 184 Left 0 ;Total = 24 transistors +Version 4 +SHEET 1 880 680 +WIRE -96 -32 -192 -32 +WIRE 48 -32 -96 -32 +WIRE 160 16 112 16 +WIRE -32 32 -192 32 +WIRE 48 32 0 32 +WIRE 160 48 160 16 +WIRE 224 48 160 48 +WIRE 224 80 160 80 +WIRE 384 80 288 80 +WIRE -32 96 -32 32 +WIRE 48 96 -32 96 +WIRE 160 144 160 80 +WIRE 160 144 112 144 +WIRE 48 160 -64 160 +WIRE -96 224 -96 -32 +WIRE 48 224 -96 224 +WIRE 160 272 112 272 +WIRE -64 288 -64 160 +WIRE 48 288 -64 288 +WIRE 160 304 160 272 +WIRE 224 304 160 304 +WIRE 224 336 160 336 +WIRE 384 336 288 336 +WIRE 0 352 0 32 +WIRE 0 352 -192 352 +WIRE 48 352 0 352 +WIRE 160 400 160 336 +WIRE 160 400 112 400 +WIRE -64 416 -64 288 +WIRE -64 416 -192 416 +WIRE -32 416 -32 96 +WIRE 48 416 -32 416 +FLAG 384 80 Y- +IOPIN 384 80 Out +FLAG 384 336 Y+ +IOPIN 384 336 Out +FLAG -192 -32 A- +IOPIN -192 -32 In +FLAG -192 32 A+ +IOPIN -192 32 In +FLAG -192 352 B- +IOPIN -192 352 In +FLAG -192 416 B+ +IOPIN -192 416 In +SYMBOL Digital\\and 80 -64 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 80 64 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 80 192 R0 +SYMATTR InstName A3 +SYMBOL Digital\\and 80 320 R0 +SYMATTR InstName A4 +SYMBOL Digital\\and 256 256 R0 +SYMATTR InstName A5 +SYMBOL Digital\\and 256 0 R0 +SYMATTR InstName A6 +TEXT 216 184 Left 0 ;Total = 24 transistors diff --git a/simulated/xor.asy b/simulated/xor.asy index a2aa152..e9cd12f 100644 --- a/simulated/xor.asy +++ b/simulated/xor.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 XOR -SYMATTR Description XOR gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 XOR +SYMATTR Description XOR gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 -- cgit