From 76682bade38a8b2d58490ddbb80cb627a2b2ad1b Mon Sep 17 00:00:00 2001 From: Jed Barber Date: Thu, 15 Dec 2016 14:26:29 +1100 Subject: Old uncommitted changes --- simulated/2_input_max.asc | 62 +++++----- simulated/2_input_max.asy | 82 ++++++------- simulated/2_input_min.asc | 62 +++++----- simulated/2_input_min.asy | 82 ++++++------- simulated/buffer.asc | 26 ++--- simulated/buffer.asy | 62 +++++----- simulated/clamp_down.asc | 32 ++--- simulated/clamp_down.asy | 66 +++++------ simulated/clamp_up.asc | 32 ++--- simulated/clamp_up.asy | 66 +++++------ simulated/consensus.asc | 62 +++++----- simulated/consensus.asy | 82 ++++++------- simulated/decrement.asc | 54 ++++----- simulated/decrement.asy | 62 +++++----- simulated/equality.asc | 102 ++++++++-------- simulated/equality.asy | 82 ++++++------- simulated/gullible.asc | 86 +++++++------- simulated/gullible.asy | 82 ++++++------- simulated/increment.asc | 54 ++++----- simulated/increment.asy | 62 +++++----- simulated/is_false.asc | 38 +++--- simulated/is_false.asy | 62 +++++----- simulated/is_true.asc | 38 +++--- simulated/is_true.asy | 62 +++++----- simulated/is_unknown.asc | 34 +++--- simulated/is_unknown.asy | 62 +++++----- simulated/negative_threshold_inverter.asc | 38 +++--- simulated/negative_threshold_inverter.asy | 64 +++++----- simulated/positive_threshold_inverter.asc | 38 +++--- simulated/positive_threshold_inverter.asy | 64 +++++----- simulated/standard_inverter.asc | 38 +++--- simulated/standard_inverter.asy | 64 +++++----- simulated/sum.asc | 188 +++++++++++++++--------------- simulated/sum.asy | 82 ++++++------- simulated/xor.asc | 118 +++++++++---------- simulated/xor.asy | 82 ++++++------- 36 files changed, 1186 insertions(+), 1186 deletions(-) (limited to 'simulated') diff --git a/simulated/2_input_max.asc b/simulated/2_input_max.asc index 52ff328..eb2493d 100644 --- a/simulated/2_input_max.asc +++ b/simulated/2_input_max.asc @@ -1,31 +1,31 @@ -Version 4 -SHEET 1 880 680 -WIRE 144 16 -32 16 -WIRE 320 32 208 32 -WIRE 64 80 -32 80 -WIRE 144 80 96 80 -WIRE 96 144 96 80 -WIRE 96 144 32 144 -WIRE 32 208 32 144 -WIRE 32 208 -32 208 -WIRE 64 208 64 80 -WIRE 144 208 64 208 -WIRE 320 224 208 224 -WIRE 144 272 -32 272 -FLAG -32 16 A- -IOPIN -32 16 In -FLAG -32 80 A+ -IOPIN -32 80 In -FLAG -32 208 B- -IOPIN -32 208 In -FLAG -32 272 B+ -IOPIN -32 272 In -FLAG 320 32 Y- -IOPIN 320 32 Out -FLAG 320 224 Y+ -IOPIN 320 224 Out -SYMBOL Digital\\or 176 176 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 176 -16 R0 -SYMATTR InstName A2 -TEXT 248 312 Left 0 ;Total = 12 transistors +Version 4 +SHEET 1 880 680 +WIRE 144 16 -32 16 +WIRE 320 32 208 32 +WIRE 64 80 -32 80 +WIRE 144 80 96 80 +WIRE 96 144 96 80 +WIRE 96 144 32 144 +WIRE 32 208 32 144 +WIRE 32 208 -32 208 +WIRE 64 208 64 80 +WIRE 144 208 64 208 +WIRE 320 224 208 224 +WIRE 144 272 -32 272 +FLAG -32 16 A- +IOPIN -32 16 In +FLAG -32 80 A+ +IOPIN -32 80 In +FLAG -32 208 B- +IOPIN -32 208 In +FLAG -32 272 B+ +IOPIN -32 272 In +FLAG 320 32 Y- +IOPIN 320 32 Out +FLAG 320 224 Y+ +IOPIN 320 224 Out +SYMBOL Digital\\or 176 176 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 176 -16 R0 +SYMATTR InstName A2 +TEXT 248 312 Left 0 ;Total = 12 transistors diff --git a/simulated/2_input_max.asy b/simulated/2_input_max.asy index f900f55..ddb4786 100644 --- a/simulated/2_input_max.asy +++ b/simulated/2_input_max.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 MAX -SYMATTR Description 2-input MAX gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 MAX +SYMATTR Description 2-input MAX gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/2_input_min.asc b/simulated/2_input_min.asc index 86179cb..37b6577 100644 --- a/simulated/2_input_min.asc +++ b/simulated/2_input_min.asc @@ -1,31 +1,31 @@ -Version 4 -SHEET 1 880 680 -WIRE 144 16 -32 16 -WIRE 320 32 208 32 -WIRE 64 80 -32 80 -WIRE 144 80 96 80 -WIRE 96 144 96 80 -WIRE 96 144 32 144 -WIRE 32 208 32 144 -WIRE 32 208 -32 208 -WIRE 64 208 64 80 -WIRE 144 208 64 208 -WIRE 320 224 208 224 -WIRE 144 272 -32 272 -FLAG -32 16 A- -IOPIN -32 16 In -FLAG -32 80 A+ -IOPIN -32 80 In -FLAG -32 208 B- -IOPIN -32 208 In -FLAG -32 272 B+ -IOPIN -32 272 In -FLAG 320 32 Y- -IOPIN 320 32 Out -FLAG 320 224 Y+ -IOPIN 320 224 Out -SYMBOL Digital\\or 176 -16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 176 176 R0 -SYMATTR InstName A2 -TEXT 248 312 Left 0 ;Total = 12 transistors +Version 4 +SHEET 1 880 680 +WIRE 144 16 -32 16 +WIRE 320 32 208 32 +WIRE 64 80 -32 80 +WIRE 144 80 96 80 +WIRE 96 144 96 80 +WIRE 96 144 32 144 +WIRE 32 208 32 144 +WIRE 32 208 -32 208 +WIRE 64 208 64 80 +WIRE 144 208 64 208 +WIRE 320 224 208 224 +WIRE 144 272 -32 272 +FLAG -32 16 A- +IOPIN -32 16 In +FLAG -32 80 A+ +IOPIN -32 80 In +FLAG -32 208 B- +IOPIN -32 208 In +FLAG -32 272 B+ +IOPIN -32 272 In +FLAG 320 32 Y- +IOPIN 320 32 Out +FLAG 320 224 Y+ +IOPIN 320 224 Out +SYMBOL Digital\\or 176 -16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 176 176 R0 +SYMATTR InstName A2 +TEXT 248 312 Left 0 ;Total = 12 transistors diff --git a/simulated/2_input_min.asy b/simulated/2_input_min.asy index ed919e3..1c442ce 100644 --- a/simulated/2_input_min.asy +++ b/simulated/2_input_min.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 MIN -SYMATTR Description 2-input MIN gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 MIN +SYMATTR Description 2-input MIN gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/buffer.asc b/simulated/buffer.asc index b1a7566..964eacf 100644 --- a/simulated/buffer.asc +++ b/simulated/buffer.asc @@ -1,13 +1,13 @@ -Version 4 -SHEET 1 880 680 -WIRE 288 96 64 96 -WIRE 288 160 64 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 288 96 64 96 +WIRE 288 160 64 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/buffer.asy b/simulated/buffer.asy index de8c658..6527b67 100644 --- a/simulated/buffer.asy +++ b/simulated/buffer.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 BUF -SYMATTR Description Buffer -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 BUF +SYMATTR Description Buffer +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/clamp_down.asc b/simulated/clamp_down.asc index ba95611..6cac961 100644 --- a/simulated/clamp_down.asc +++ b/simulated/clamp_down.asc @@ -1,16 +1,16 @@ -Version 4 -SHEET 1 880 680 -WIRE 288 96 64 96 -WIRE 128 160 64 160 -WIRE 288 160 176 160 -WIRE 176 176 176 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -FLAG 176 176 0 -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 288 96 64 96 +WIRE 128 160 64 160 +WIRE 288 160 176 160 +WIRE 176 176 176 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +FLAG 176 176 0 +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/clamp_down.asy b/simulated/clamp_down.asy index 44deb75..c3fb2fe 100644 --- a/simulated/clamp_down.asy +++ b/simulated/clamp_down.asy @@ -1,33 +1,33 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -64 48 -48 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 64 80 64 64 -LINE Normal 80 80 64 80 -TEXT 1 48 Center 0 MIN -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP DOWN gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN 80 80 NONE 0 -PINATTR PinName Y+ -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 8 -PINATTR PinName Y- -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -64 48 -48 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 64 80 64 64 +LINE Normal 80 80 64 80 +TEXT 1 48 Center 0 MIN +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP DOWN gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN 80 80 NONE 0 +PINATTR PinName Y+ +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 8 +PINATTR PinName Y- +PINATTR SpiceOrder 4 diff --git a/simulated/clamp_up.asc b/simulated/clamp_up.asc index e260cad..59563e5 100644 --- a/simulated/clamp_up.asc +++ b/simulated/clamp_up.asc @@ -1,16 +1,16 @@ -Version 4 -SHEET 1 880 680 -WIRE 128 96 64 96 -WIRE 288 96 176 96 -WIRE 176 112 176 96 -WIRE 288 160 64 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -FLAG 176 112 0 -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 128 96 64 96 +WIRE 288 96 176 96 +WIRE 176 112 176 96 +WIRE 288 160 64 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +FLAG 176 112 0 +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/clamp_up.asy b/simulated/clamp_up.asy index 26415b5..c5ed36e 100644 --- a/simulated/clamp_up.asy +++ b/simulated/clamp_up.asy @@ -1,33 +1,33 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -64 48 -48 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 64 80 64 64 -LINE Normal 80 80 64 80 -TEXT 1 48 Center 0 MAX -TEXT -63 80 Left 0 0 -SYMATTR Description CLAMP UP gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN 80 80 NONE 0 -PINATTR PinName Y+ -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 8 -PINATTR PinName Y- -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -64 48 -48 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 64 80 64 64 +LINE Normal 80 80 64 80 +TEXT 1 48 Center 0 MAX +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP UP gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN 80 80 NONE 0 +PINATTR PinName Y+ +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 8 +PINATTR PinName Y- +PINATTR SpiceOrder 4 diff --git a/simulated/consensus.asc b/simulated/consensus.asc index 6569a51..5b41ef4 100644 --- a/simulated/consensus.asc +++ b/simulated/consensus.asc @@ -1,31 +1,31 @@ -Version 4 -SHEET 1 880 680 -WIRE 144 16 -32 16 -WIRE 320 32 208 32 -WIRE 64 80 -32 80 -WIRE 144 80 96 80 -WIRE 96 144 96 80 -WIRE 96 144 32 144 -WIRE 32 208 32 144 -WIRE 32 208 -32 208 -WIRE 64 208 64 80 -WIRE 144 208 64 208 -WIRE 320 224 208 224 -WIRE 144 272 -32 272 -FLAG -32 16 A- -IOPIN -32 16 In -FLAG -32 80 A+ -IOPIN -32 80 In -FLAG -32 208 B- -IOPIN -32 208 In -FLAG -32 272 B+ -IOPIN -32 272 In -FLAG 320 32 Y- -IOPIN 320 32 Out -FLAG 320 224 Y+ -IOPIN 320 224 Out -SYMBOL Digital\\and 176 176 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 176 -16 R0 -SYMATTR InstName A1 -TEXT 248 312 Left 0 ;Total = 12 transistors +Version 4 +SHEET 1 880 680 +WIRE 144 16 -32 16 +WIRE 320 32 208 32 +WIRE 64 80 -32 80 +WIRE 144 80 96 80 +WIRE 96 144 96 80 +WIRE 96 144 32 144 +WIRE 32 208 32 144 +WIRE 32 208 -32 208 +WIRE 64 208 64 80 +WIRE 144 208 64 208 +WIRE 320 224 208 224 +WIRE 144 272 -32 272 +FLAG -32 16 A- +IOPIN -32 16 In +FLAG -32 80 A+ +IOPIN -32 80 In +FLAG -32 208 B- +IOPIN -32 208 In +FLAG -32 272 B+ +IOPIN -32 272 In +FLAG 320 32 Y- +IOPIN 320 32 Out +FLAG 320 224 Y+ +IOPIN 320 224 Out +SYMBOL Digital\\and 176 176 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 176 -16 R0 +SYMATTR InstName A1 +TEXT 248 312 Left 0 ;Total = 12 transistors diff --git a/simulated/consensus.asy b/simulated/consensus.asy index 03c6620..1b7a24d 100644 --- a/simulated/consensus.asy +++ b/simulated/consensus.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 CON -SYMATTR Description 2-input consensus gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 CON +SYMATTR Description 2-input consensus gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/decrement.asc b/simulated/decrement.asc index cb2d762..9f3c06b 100644 --- a/simulated/decrement.asc +++ b/simulated/decrement.asc @@ -1,27 +1,27 @@ -Version 4 -SHEET 1 880 680 -WIRE 112 48 -128 48 -WIRE 240 96 176 96 -WIRE 320 96 240 96 -WIRE 112 112 -48 112 -WIRE 240 176 240 96 -WIRE 240 176 64 176 -WIRE 64 224 64 176 -WIRE 112 224 64 224 -WIRE 320 272 176 272 -WIRE -48 288 -48 112 -WIRE -48 288 -128 288 -WIRE 112 288 -48 288 -FLAG -128 48 A- -IOPIN -128 48 In -FLAG -128 288 A+ -IOPIN -128 288 In -FLAG 320 96 Y- -IOPIN 320 96 Out -FLAG 320 272 Y+ -IOPIN 320 272 Out -SYMBOL Digital\\or 144 16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 144 192 R0 -SYMATTR InstName A2 -TEXT 168 344 Left 0 ;Total = 8 transistors +Version 4 +SHEET 1 880 680 +WIRE 112 48 -128 48 +WIRE 240 96 176 96 +WIRE 320 96 240 96 +WIRE 112 112 -48 112 +WIRE 240 176 240 96 +WIRE 240 176 64 176 +WIRE 64 224 64 176 +WIRE 112 224 64 224 +WIRE 320 272 176 272 +WIRE -48 288 -48 112 +WIRE -48 288 -128 288 +WIRE 112 288 -48 288 +FLAG -128 48 A- +IOPIN -128 48 In +FLAG -128 288 A+ +IOPIN -128 288 In +FLAG 320 96 Y- +IOPIN 320 96 Out +FLAG 320 272 Y+ +IOPIN 320 272 Out +SYMBOL Digital\\or 144 16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 144 192 R0 +SYMATTR InstName A2 +TEXT 168 344 Left 0 ;Total = 8 transistors diff --git a/simulated/decrement.asy b/simulated/decrement.asy index 7405a55..a8b80f8 100644 --- a/simulated/decrement.asy +++ b/simulated/decrement.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 -1 -SYMATTR Description DECREMENT gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 -1 +SYMATTR Description DECREMENT gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/equality.asc b/simulated/equality.asc index cf3927e..4c3e0a0 100644 --- a/simulated/equality.asc +++ b/simulated/equality.asc @@ -1,51 +1,51 @@ -Version 4 -SHEET 1 880 680 -WIRE -112 -16 -160 -16 -WIRE 32 -16 -112 -16 -WIRE 160 32 96 32 -WIRE -48 48 -160 48 -WIRE 32 48 -16 48 -WIRE -48 128 -48 48 -WIRE 32 128 -48 128 -WIRE 160 128 160 32 -WIRE 224 128 160 128 -WIRE 368 144 288 144 -WIRE 224 160 144 160 -WIRE 144 176 144 160 -WIRE 144 176 96 176 -WIRE 368 176 288 176 -WIRE 32 192 -80 192 -WIRE 224 192 160 192 -WIRE -16 272 -16 48 -WIRE -16 272 -160 272 -WIRE 32 272 -16 272 -WIRE -112 288 -112 -16 -WIRE 32 288 -112 288 -WIRE 160 288 160 192 -WIRE 160 288 96 288 -WIRE -48 320 -48 128 -WIRE 32 320 -48 320 -WIRE -80 336 -80 192 -WIRE -80 336 -160 336 -WIRE 32 336 -80 336 -FLAG 368 144 Y- -IOPIN 368 144 Out -FLAG 368 176 Y+ -IOPIN 368 176 Out -FLAG -160 -16 A- -IOPIN -160 -16 In -FLAG -160 48 A+ -IOPIN -160 48 In -FLAG -160 272 B- -IOPIN -160 272 In -FLAG -160 336 B+ -IOPIN -160 336 In -SYMBOL Digital\\and 256 96 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 64 96 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 64 -48 R0 -SYMATTR InstName A3 -SYMBOL Digital\\or 64 240 R0 -SYMATTR InstName A4 -TEXT 224 272 Left 0 ;Total = 26 transistors +Version 4 +SHEET 1 880 680 +WIRE -112 -16 -160 -16 +WIRE 32 -16 -112 -16 +WIRE 160 32 96 32 +WIRE -48 48 -160 48 +WIRE 32 48 -16 48 +WIRE -48 128 -48 48 +WIRE 32 128 -48 128 +WIRE 160 128 160 32 +WIRE 224 128 160 128 +WIRE 368 144 288 144 +WIRE 224 160 144 160 +WIRE 144 176 144 160 +WIRE 144 176 96 176 +WIRE 368 176 288 176 +WIRE 32 192 -80 192 +WIRE 224 192 160 192 +WIRE -16 272 -16 48 +WIRE -16 272 -160 272 +WIRE 32 272 -16 272 +WIRE -112 288 -112 -16 +WIRE 32 288 -112 288 +WIRE 160 288 160 192 +WIRE 160 288 96 288 +WIRE -48 320 -48 128 +WIRE 32 320 -48 320 +WIRE -80 336 -80 192 +WIRE -80 336 -160 336 +WIRE 32 336 -80 336 +FLAG 368 144 Y- +IOPIN 368 144 Out +FLAG 368 176 Y+ +IOPIN 368 176 Out +FLAG -160 -16 A- +IOPIN -160 -16 In +FLAG -160 48 A+ +IOPIN -160 48 In +FLAG -160 272 B- +IOPIN -160 272 In +FLAG -160 336 B+ +IOPIN -160 336 In +SYMBOL Digital\\and 256 96 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 64 96 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 64 -48 R0 +SYMATTR InstName A3 +SYMBOL Digital\\or 64 240 R0 +SYMATTR InstName A4 +TEXT 224 272 Left 0 ;Total = 26 transistors diff --git a/simulated/equality.asy b/simulated/equality.asy index 1c81763..8f852e1 100644 --- a/simulated/equality.asy +++ b/simulated/equality.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 = -SYMATTR Description 2-input equality gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 = +SYMATTR Description 2-input equality gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/gullible.asc b/simulated/gullible.asc index 0589e69..8e0a2bd 100644 --- a/simulated/gullible.asc +++ b/simulated/gullible.asc @@ -1,43 +1,43 @@ -Version 4 -SHEET 1 880 680 -WIRE 64 48 -96 48 -WIRE 192 64 128 64 -WIRE 224 96 128 96 -WIRE 368 96 288 96 -WIRE -48 112 -96 112 -WIRE 64 112 -16 112 -WIRE 224 112 160 112 -WIRE -48 176 -48 112 -WIRE 16 176 -48 176 -WIRE -16 240 -16 112 -WIRE -16 240 -96 240 -WIRE 16 240 16 176 -WIRE 64 240 16 240 -WIRE 192 240 192 64 -WIRE 224 240 192 240 -WIRE 160 256 160 112 -WIRE 160 256 128 256 -WIRE 224 288 128 288 -WIRE 368 288 288 288 -WIRE 64 304 -96 304 -FLAG -96 112 A+ -IOPIN -96 112 In -FLAG -96 48 A- -IOPIN -96 48 In -FLAG -96 240 B- -IOPIN -96 240 In -FLAG -96 304 B+ -IOPIN -96 304 In -FLAG 368 96 Y- -IOPIN 368 96 Out -FLAG 368 288 Y+ -IOPIN 368 288 Out -SYMBOL Digital\\or 96 16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 96 208 R0 -SYMATTR InstName A2 -SYMBOL Digital\\or 256 16 R0 -SYMATTR InstName A3 -SYMBOL Digital\\or 256 208 R0 -SYMATTR InstName A4 -TEXT 232 384 Left 0 ;Total = 20 transistors +Version 4 +SHEET 1 880 680 +WIRE 64 48 -96 48 +WIRE 192 64 128 64 +WIRE 224 96 128 96 +WIRE 368 96 288 96 +WIRE -48 112 -96 112 +WIRE 64 112 -16 112 +WIRE 224 112 160 112 +WIRE -48 176 -48 112 +WIRE 16 176 -48 176 +WIRE -16 240 -16 112 +WIRE -16 240 -96 240 +WIRE 16 240 16 176 +WIRE 64 240 16 240 +WIRE 192 240 192 64 +WIRE 224 240 192 240 +WIRE 160 256 160 112 +WIRE 160 256 128 256 +WIRE 224 288 128 288 +WIRE 368 288 288 288 +WIRE 64 304 -96 304 +FLAG -96 112 A+ +IOPIN -96 112 In +FLAG -96 48 A- +IOPIN -96 48 In +FLAG -96 240 B- +IOPIN -96 240 In +FLAG -96 304 B+ +IOPIN -96 304 In +FLAG 368 96 Y- +IOPIN 368 96 Out +FLAG 368 288 Y+ +IOPIN 368 288 Out +SYMBOL Digital\\or 96 16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 96 208 R0 +SYMATTR InstName A2 +SYMBOL Digital\\or 256 16 R0 +SYMATTR InstName A3 +SYMBOL Digital\\or 256 208 R0 +SYMATTR InstName A4 +TEXT 232 384 Left 0 ;Total = 20 transistors diff --git a/simulated/gullible.asy b/simulated/gullible.asy index d7cf229..5bb7f99 100644 --- a/simulated/gullible.asy +++ b/simulated/gullible.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 GUL -SYMATTR Description 2-input gullible gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 GUL +SYMATTR Description 2-input gullible gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/increment.asc b/simulated/increment.asc index f2f5fcb..f387838 100644 --- a/simulated/increment.asc +++ b/simulated/increment.asc @@ -1,27 +1,27 @@ -Version 4 -SHEET 1 880 680 -WIRE -48 48 -128 48 -WIRE 112 48 -48 48 -WIRE 320 96 176 96 -WIRE 112 112 64 112 -WIRE 64 176 64 112 -WIRE 240 176 64 176 -WIRE -48 224 -48 48 -WIRE 112 224 -48 224 -WIRE 240 272 240 176 -WIRE 240 272 176 272 -WIRE 320 272 240 272 -WIRE 112 288 -128 288 -FLAG -128 48 A- -IOPIN -128 48 In -FLAG -128 288 A+ -IOPIN -128 288 In -FLAG 320 96 Y- -IOPIN 320 96 Out -FLAG 320 272 Y+ -IOPIN 320 272 Out -SYMBOL Digital\\or 144 16 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 144 192 R0 -SYMATTR InstName A2 -TEXT 168 344 Left 0 ;Total = 8 transistors +Version 4 +SHEET 1 880 680 +WIRE -48 48 -128 48 +WIRE 112 48 -48 48 +WIRE 320 96 176 96 +WIRE 112 112 64 112 +WIRE 64 176 64 112 +WIRE 240 176 64 176 +WIRE -48 224 -48 48 +WIRE 112 224 -48 224 +WIRE 240 272 240 176 +WIRE 240 272 176 272 +WIRE 320 272 240 272 +WIRE 112 288 -128 288 +FLAG -128 48 A- +IOPIN -128 48 In +FLAG -128 288 A+ +IOPIN -128 288 In +FLAG 320 96 Y- +IOPIN 320 96 Out +FLAG 320 272 Y+ +IOPIN 320 272 Out +SYMBOL Digital\\or 144 16 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 144 192 R0 +SYMATTR InstName A2 +TEXT 168 344 Left 0 ;Total = 8 transistors diff --git a/simulated/increment.asy b/simulated/increment.asy index bb089d8..41cc792 100644 --- a/simulated/increment.asy +++ b/simulated/increment.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 +1 -SYMATTR Description INCREMENT gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 +1 +SYMATTR Description INCREMENT gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/is_false.asc b/simulated/is_false.asc index 8d7d1d6..bfb6e2e 100644 --- a/simulated/is_false.asc +++ b/simulated/is_false.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 32 64 -48 64 -WIRE 96 64 32 64 -WIRE 240 64 160 64 -WIRE 0 128 -48 128 -WIRE 32 128 32 64 -WIRE 240 128 32 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 0 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 32 64 -48 64 +WIRE 96 64 32 64 +WIRE 240 64 160 64 +WIRE 0 128 -48 128 +WIRE 32 128 32 64 +WIRE 240 128 32 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 0 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/is_false.asy b/simulated/is_false.asy index e0ff789..2f21c93 100644 --- a/simulated/is_false.asy +++ b/simulated/is_false.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 =- -SYMATTR Description IS FALSE gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 =- +SYMATTR Description IS FALSE gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/is_true.asc b/simulated/is_true.asc index 0839114..7a133be 100644 --- a/simulated/is_true.asc +++ b/simulated/is_true.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 0 64 -48 64 -WIRE 96 64 32 64 -WIRE 240 64 160 64 -WIRE 32 128 32 64 -WIRE 32 128 -48 128 -WIRE 240 128 32 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 0 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 0 64 -48 64 +WIRE 96 64 32 64 +WIRE 240 64 160 64 +WIRE 32 128 32 64 +WIRE 32 128 -48 128 +WIRE 240 128 32 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 0 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/is_true.asy b/simulated/is_true.asy index aced3f6..cddae6b 100644 --- a/simulated/is_true.asy +++ b/simulated/is_true.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 =+ -SYMATTR Description IS TRUE gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 =+ +SYMATTR Description IS TRUE gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/is_unknown.asc b/simulated/is_unknown.asc index bc40aa2..e33ac33 100644 --- a/simulated/is_unknown.asc +++ b/simulated/is_unknown.asc @@ -1,17 +1,17 @@ -Version 4 -SHEET 1 880 680 -WIRE 64 64 -48 64 -WIRE 240 80 128 80 -WIRE 240 112 128 112 -WIRE 64 128 -48 128 -FLAG 240 80 Y- -IOPIN 240 80 Out -FLAG 240 112 Y+ -IOPIN 240 112 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\or 96 32 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 6 transistors +Version 4 +SHEET 1 880 680 +WIRE 64 64 -48 64 +WIRE 240 80 128 80 +WIRE 240 112 128 112 +WIRE 64 128 -48 128 +FLAG 240 80 Y- +IOPIN 240 80 Out +FLAG 240 112 Y+ +IOPIN 240 112 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\or 96 32 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 6 transistors diff --git a/simulated/is_unknown.asy b/simulated/is_unknown.asy index 40fc34a..a838309 100644 --- a/simulated/is_unknown.asy +++ b/simulated/is_unknown.asy @@ -1,31 +1,31 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 =0 -SYMATTR Description IS UNKNOWN gate -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 =0 +SYMATTR Description IS UNKNOWN gate +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/negative_threshold_inverter.asc b/simulated/negative_threshold_inverter.asc index 8d7d1d6..bfb6e2e 100644 --- a/simulated/negative_threshold_inverter.asc +++ b/simulated/negative_threshold_inverter.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 32 64 -48 64 -WIRE 96 64 32 64 -WIRE 240 64 160 64 -WIRE 0 128 -48 128 -WIRE 32 128 32 64 -WIRE 240 128 32 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 0 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 32 64 -48 64 +WIRE 96 64 32 64 +WIRE 240 64 160 64 +WIRE 0 128 -48 128 +WIRE 32 128 32 64 +WIRE 240 128 32 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 0 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/negative_threshold_inverter.asy b/simulated/negative_threshold_inverter.asy index 88aa7bd..8e0c1f5 100644 --- a/simulated/negative_threshold_inverter.asy +++ b/simulated/negative_threshold_inverter.asy @@ -1,32 +1,32 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 NTI -SYMATTR Description Negative threshold inverter -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 NTI +SYMATTR Description Negative threshold inverter +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/positive_threshold_inverter.asc b/simulated/positive_threshold_inverter.asc index 983226c..4daed9d 100644 --- a/simulated/positive_threshold_inverter.asc +++ b/simulated/positive_threshold_inverter.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 0 64 -48 64 -WIRE 240 64 32 64 -WIRE 32 128 32 64 -WIRE 32 128 -48 128 -WIRE 96 128 32 128 -WIRE 240 128 160 128 -FLAG 240 64 Y- -IOPIN 240 64 Out -FLAG 240 128 Y+ -IOPIN 240 128 Out -FLAG -48 64 A- -IOPIN -48 64 In -FLAG -48 128 A+ -IOPIN -48 128 In -SYMBOL Digital\\inv 96 64 R0 -SYMATTR InstName A1 -TEXT 144 216 Left 0 ;Total = 2 transistors +Version 4 +SHEET 1 880 680 +WIRE 0 64 -48 64 +WIRE 240 64 32 64 +WIRE 32 128 32 64 +WIRE 32 128 -48 128 +WIRE 96 128 32 128 +WIRE 240 128 160 128 +FLAG 240 64 Y- +IOPIN 240 64 Out +FLAG 240 128 Y+ +IOPIN 240 128 Out +FLAG -48 64 A- +IOPIN -48 64 In +FLAG -48 128 A+ +IOPIN -48 128 In +SYMBOL Digital\\inv 96 64 R0 +SYMATTR InstName A1 +TEXT 144 216 Left 0 ;Total = 2 transistors diff --git a/simulated/positive_threshold_inverter.asy b/simulated/positive_threshold_inverter.asy index a180db8..9eeb9e2 100644 --- a/simulated/positive_threshold_inverter.asy +++ b/simulated/positive_threshold_inverter.asy @@ -1,32 +1,32 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 PTI -SYMATTR Description Positive threshold inverter -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 PTI +SYMATTR Description Positive threshold inverter +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/standard_inverter.asc b/simulated/standard_inverter.asc index a0a58b0..8c4f4a5 100644 --- a/simulated/standard_inverter.asc +++ b/simulated/standard_inverter.asc @@ -1,19 +1,19 @@ -Version 4 -SHEET 1 880 680 -WIRE 176 96 64 96 -WIRE 288 96 208 96 -WIRE 208 128 208 96 -WIRE 208 128 144 128 -WIRE 144 160 144 128 -WIRE 144 160 64 160 -WIRE 176 160 176 96 -WIRE 288 160 176 160 -FLAG 64 96 A- -IOPIN 64 96 In -FLAG 64 160 A+ -IOPIN 64 160 In -FLAG 288 96 Y- -IOPIN 288 96 Out -FLAG 288 160 Y+ -IOPIN 288 160 Out -TEXT 136 232 Left 0 ;Total = 0 transistors +Version 4 +SHEET 1 880 680 +WIRE 176 96 64 96 +WIRE 288 96 208 96 +WIRE 208 128 208 96 +WIRE 208 128 144 128 +WIRE 144 160 144 128 +WIRE 144 160 64 160 +WIRE 176 160 176 96 +WIRE 288 160 176 160 +FLAG 64 96 A- +IOPIN 64 96 In +FLAG 64 160 A+ +IOPIN 64 160 In +FLAG 288 96 Y- +IOPIN 288 96 Out +FLAG 288 160 Y+ +IOPIN 288 160 Out +TEXT 136 232 Left 0 ;Total = 0 transistors diff --git a/simulated/standard_inverter.asy b/simulated/standard_inverter.asy index 4a10402..d43138c 100644 --- a/simulated/standard_inverter.asy +++ b/simulated/standard_inverter.asy @@ -1,32 +1,32 @@ -Version 4 -SymbolType CELL -LINE Normal 32 48 64 48 -LINE Normal -32 48 -48 48 -LINE Normal 32 32 -32 32 -LINE Normal 32 64 32 32 -LINE Normal -32 64 32 64 -LINE Normal -32 32 -32 64 -LINE Normal 32 40 32 48 -LINE Normal 47 48 32 40 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -48 64 -48 48 -LINE Normal -64 64 -48 64 -LINE Normal 80 32 64 32 -LINE Normal 64 64 64 48 -LINE Normal 80 64 64 64 -LINE Normal 64 32 64 48 -TEXT 0 48 Center 0 NEG -SYMATTR Description Inverter -PIN -64 32 NONE 0 -PINATTR PinName A- -PINATTR SpiceOrder 1 -PIN 80 32 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 2 -PIN -64 64 NONE 8 -PINATTR PinName A+ -PINATTR SpiceOrder 3 -PIN 80 64 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 4 +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -48 64 -48 48 +LINE Normal -64 64 -48 64 +LINE Normal 80 32 64 32 +LINE Normal 64 64 64 48 +LINE Normal 80 64 64 64 +LINE Normal 64 32 64 48 +TEXT 0 48 Center 0 NEG +SYMATTR Description Inverter +PIN -64 32 NONE 0 +PINATTR PinName A- +PINATTR SpiceOrder 1 +PIN 80 32 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 2 +PIN -64 64 NONE 8 +PINATTR PinName A+ +PINATTR SpiceOrder 3 +PIN 80 64 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 4 diff --git a/simulated/sum.asc b/simulated/sum.asc index 8edf7a5..7d520c3 100644 --- a/simulated/sum.asc +++ b/simulated/sum.asc @@ -1,94 +1,94 @@ -Version 4 -SHEET 1 880 680 -WIRE 160 -224 -176 -224 -WIRE 320 -176 224 -176 -WIRE 160 -160 -144 -160 -WIRE 160 -96 -112 -96 -WIRE 112 -64 -80 -64 -WIRE 288 -48 224 -48 -WIRE 160 -32 80 -32 -WIRE -112 32 -112 -96 -WIRE -112 32 -256 32 -WIRE -32 32 -112 32 -WIRE 112 32 112 -64 -WIRE 160 32 112 32 -WIRE 320 32 320 -176 -WIRE 352 32 320 32 -WIRE 288 64 288 -48 -WIRE 352 64 288 64 -WIRE 112 80 32 80 -WIRE 256 80 224 80 -WIRE 528 80 416 80 -WIRE -144 96 -144 -160 -WIRE -144 96 -256 96 -WIRE -32 96 -144 96 -WIRE 112 96 112 80 -WIRE 160 96 112 96 -WIRE 256 96 256 80 -WIRE 352 96 256 96 -WIRE -80 176 -80 -64 -WIRE -80 176 -256 176 -WIRE -32 176 -80 176 -WIRE 112 176 112 96 -WIRE 160 176 112 176 -WIRE 352 176 256 176 -WIRE 352 208 288 208 -WIRE 80 224 80 -32 -WIRE 80 224 32 224 -WIRE 256 224 256 176 -WIRE 256 224 224 224 -WIRE 528 224 416 224 -WIRE -208 240 -256 240 -WIRE -176 240 -176 -224 -WIRE -176 240 -208 240 -WIRE -32 240 -176 240 -WIRE 160 240 112 240 -WIRE 352 240 320 240 -WIRE 80 304 80 224 -WIRE 160 304 80 304 -WIRE -208 336 -208 240 -WIRE 112 336 112 240 -WIRE 112 336 -208 336 -WIRE 288 352 288 208 -WIRE 288 352 224 352 -WIRE -144 368 -144 96 -WIRE 160 368 -144 368 -WIRE -112 432 -112 32 -WIRE 160 432 -112 432 -WIRE 320 480 320 240 -WIRE 320 480 224 480 -WIRE -80 496 -80 176 -WIRE 160 496 -80 496 -FLAG 528 80 Y- -IOPIN 528 80 Out -FLAG 528 224 Y+ -IOPIN 528 224 Out -FLAG -256 32 A- -IOPIN -256 32 In -FLAG -256 96 A+ -IOPIN -256 96 In -FLAG -256 176 B- -IOPIN -256 176 In -FLAG -256 240 B+ -IOPIN -256 240 In -SYMBOL Digital\\or 0 0 R0 -SYMATTR InstName A1 -SYMBOL Digital\\or 0 144 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 192 0 R0 -SYMATTR InstName A3 -SYMBOL Digital\\and 192 144 R0 -SYMATTR InstName A4 -SYMBOL Digital\\and 192 -128 R0 -SYMATTR InstName A5 -SYMBOL Digital\\and 192 -256 R0 -SYMATTR InstName A6 -SYMBOL Digital\\and 192 272 R0 -SYMATTR InstName A7 -SYMBOL Digital\\and 192 400 R0 -SYMATTR InstName A8 -SYMBOL Digital\\and 384 144 R0 -SYMATTR InstName A9 -SYMBOL Digital\\and 384 0 R0 -SYMATTR InstName A10 -TEXT 408 328 Left 0 ;Total = 44 transistors +Version 4 +SHEET 1 880 680 +WIRE 160 -224 -176 -224 +WIRE 320 -176 224 -176 +WIRE 160 -160 -144 -160 +WIRE 160 -96 -112 -96 +WIRE 112 -64 -80 -64 +WIRE 288 -48 224 -48 +WIRE 160 -32 80 -32 +WIRE -112 32 -112 -96 +WIRE -112 32 -256 32 +WIRE -32 32 -112 32 +WIRE 112 32 112 -64 +WIRE 160 32 112 32 +WIRE 320 32 320 -176 +WIRE 352 32 320 32 +WIRE 288 64 288 -48 +WIRE 352 64 288 64 +WIRE 112 80 32 80 +WIRE 256 80 224 80 +WIRE 528 80 416 80 +WIRE -144 96 -144 -160 +WIRE -144 96 -256 96 +WIRE -32 96 -144 96 +WIRE 112 96 112 80 +WIRE 160 96 112 96 +WIRE 256 96 256 80 +WIRE 352 96 256 96 +WIRE -80 176 -80 -64 +WIRE -80 176 -256 176 +WIRE -32 176 -80 176 +WIRE 112 176 112 96 +WIRE 160 176 112 176 +WIRE 352 176 256 176 +WIRE 352 208 288 208 +WIRE 80 224 80 -32 +WIRE 80 224 32 224 +WIRE 256 224 256 176 +WIRE 256 224 224 224 +WIRE 528 224 416 224 +WIRE -208 240 -256 240 +WIRE -176 240 -176 -224 +WIRE -176 240 -208 240 +WIRE -32 240 -176 240 +WIRE 160 240 112 240 +WIRE 352 240 320 240 +WIRE 80 304 80 224 +WIRE 160 304 80 304 +WIRE -208 336 -208 240 +WIRE 112 336 112 240 +WIRE 112 336 -208 336 +WIRE 288 352 288 208 +WIRE 288 352 224 352 +WIRE -144 368 -144 96 +WIRE 160 368 -144 368 +WIRE -112 432 -112 32 +WIRE 160 432 -112 432 +WIRE 320 480 320 240 +WIRE 320 480 224 480 +WIRE -80 496 -80 176 +WIRE 160 496 -80 496 +FLAG 528 80 Y- +IOPIN 528 80 Out +FLAG 528 224 Y+ +IOPIN 528 224 Out +FLAG -256 32 A- +IOPIN -256 32 In +FLAG -256 96 A+ +IOPIN -256 96 In +FLAG -256 176 B- +IOPIN -256 176 In +FLAG -256 240 B+ +IOPIN -256 240 In +SYMBOL Digital\\or 0 0 R0 +SYMATTR InstName A1 +SYMBOL Digital\\or 0 144 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 192 0 R0 +SYMATTR InstName A3 +SYMBOL Digital\\and 192 144 R0 +SYMATTR InstName A4 +SYMBOL Digital\\and 192 -128 R0 +SYMATTR InstName A5 +SYMBOL Digital\\and 192 -256 R0 +SYMATTR InstName A6 +SYMBOL Digital\\and 192 272 R0 +SYMATTR InstName A7 +SYMBOL Digital\\and 192 400 R0 +SYMATTR InstName A8 +SYMBOL Digital\\and 384 144 R0 +SYMATTR InstName A9 +SYMBOL Digital\\and 384 0 R0 +SYMATTR InstName A10 +TEXT 408 328 Left 0 ;Total = 44 transistors diff --git a/simulated/sum.asy b/simulated/sum.asy index f72c0e1..c9e9227 100644 --- a/simulated/sum.asy +++ b/simulated/sum.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 SUM -SYMATTR Description SUM gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 SUM +SYMATTR Description SUM gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 diff --git a/simulated/xor.asc b/simulated/xor.asc index fdc5ed7..16ebdc7 100644 --- a/simulated/xor.asc +++ b/simulated/xor.asc @@ -1,59 +1,59 @@ -Version 4 -SHEET 1 880 680 -WIRE -96 -32 -192 -32 -WIRE 48 -32 -96 -32 -WIRE 160 16 112 16 -WIRE -32 32 -192 32 -WIRE 48 32 0 32 -WIRE 160 48 160 16 -WIRE 224 48 160 48 -WIRE 224 80 160 80 -WIRE 384 80 288 80 -WIRE -32 96 -32 32 -WIRE 48 96 -32 96 -WIRE 160 144 160 80 -WIRE 160 144 112 144 -WIRE 48 160 -64 160 -WIRE -96 224 -96 -32 -WIRE 48 224 -96 224 -WIRE 160 272 112 272 -WIRE -64 288 -64 160 -WIRE 48 288 -64 288 -WIRE 160 304 160 272 -WIRE 224 304 160 304 -WIRE 224 336 160 336 -WIRE 384 336 288 336 -WIRE 0 352 0 32 -WIRE 0 352 -192 352 -WIRE 48 352 0 352 -WIRE 160 400 160 336 -WIRE 160 400 112 400 -WIRE -64 416 -64 288 -WIRE -64 416 -192 416 -WIRE -32 416 -32 96 -WIRE 48 416 -32 416 -FLAG 384 80 Y- -IOPIN 384 80 Out -FLAG 384 336 Y+ -IOPIN 384 336 Out -FLAG -192 -32 A- -IOPIN -192 -32 In -FLAG -192 32 A+ -IOPIN -192 32 In -FLAG -192 352 B- -IOPIN -192 352 In -FLAG -192 416 B+ -IOPIN -192 416 In -SYMBOL Digital\\and 80 -64 R0 -SYMATTR InstName A1 -SYMBOL Digital\\and 80 64 R0 -SYMATTR InstName A2 -SYMBOL Digital\\and 80 192 R0 -SYMATTR InstName A3 -SYMBOL Digital\\and 80 320 R0 -SYMATTR InstName A4 -SYMBOL Digital\\and 256 256 R0 -SYMATTR InstName A5 -SYMBOL Digital\\and 256 0 R0 -SYMATTR InstName A6 -TEXT 216 184 Left 0 ;Total = 24 transistors +Version 4 +SHEET 1 880 680 +WIRE -96 -32 -192 -32 +WIRE 48 -32 -96 -32 +WIRE 160 16 112 16 +WIRE -32 32 -192 32 +WIRE 48 32 0 32 +WIRE 160 48 160 16 +WIRE 224 48 160 48 +WIRE 224 80 160 80 +WIRE 384 80 288 80 +WIRE -32 96 -32 32 +WIRE 48 96 -32 96 +WIRE 160 144 160 80 +WIRE 160 144 112 144 +WIRE 48 160 -64 160 +WIRE -96 224 -96 -32 +WIRE 48 224 -96 224 +WIRE 160 272 112 272 +WIRE -64 288 -64 160 +WIRE 48 288 -64 288 +WIRE 160 304 160 272 +WIRE 224 304 160 304 +WIRE 224 336 160 336 +WIRE 384 336 288 336 +WIRE 0 352 0 32 +WIRE 0 352 -192 352 +WIRE 48 352 0 352 +WIRE 160 400 160 336 +WIRE 160 400 112 400 +WIRE -64 416 -64 288 +WIRE -64 416 -192 416 +WIRE -32 416 -32 96 +WIRE 48 416 -32 416 +FLAG 384 80 Y- +IOPIN 384 80 Out +FLAG 384 336 Y+ +IOPIN 384 336 Out +FLAG -192 -32 A- +IOPIN -192 -32 In +FLAG -192 32 A+ +IOPIN -192 32 In +FLAG -192 352 B- +IOPIN -192 352 In +FLAG -192 416 B+ +IOPIN -192 416 In +SYMBOL Digital\\and 80 -64 R0 +SYMATTR InstName A1 +SYMBOL Digital\\and 80 64 R0 +SYMATTR InstName A2 +SYMBOL Digital\\and 80 192 R0 +SYMATTR InstName A3 +SYMBOL Digital\\and 80 320 R0 +SYMATTR InstName A4 +SYMBOL Digital\\and 256 256 R0 +SYMATTR InstName A5 +SYMBOL Digital\\and 256 0 R0 +SYMATTR InstName A6 +TEXT 216 184 Left 0 ;Total = 24 transistors diff --git a/simulated/xor.asy b/simulated/xor.asy index a2aa152..e9cd12f 100644 --- a/simulated/xor.asy +++ b/simulated/xor.asy @@ -1,41 +1,41 @@ -Version 4 -SymbolType CELL -LINE Normal 48 64 32 64 -LINE Normal 32 64 32 56 -LINE Normal 64 64 48 64 -LINE Normal -32 48 -48 48 -LINE Normal -32 80 -48 80 -LINE Normal 32 32 -32 32 -LINE Normal 32 96 32 32 -LINE Normal -32 96 32 96 -LINE Normal -32 32 -32 96 -LINE Normal -48 32 -48 48 -LINE Normal -64 32 -48 32 -LINE Normal -64 48 -48 48 -LINE Normal -48 96 -48 80 -LINE Normal -64 96 -48 96 -LINE Normal -64 80 -48 80 -LINE Normal 64 48 64 64 -LINE Normal 80 48 64 48 -LINE Normal 80 80 64 80 -LINE Normal 64 80 64 64 -TEXT 1 48 Center 0 XOR -SYMATTR Description XOR gate -PIN -64 48 NONE 0 -PINATTR PinName A+ -PINATTR SpiceOrder 1 -PIN -64 80 NONE 0 -PINATTR PinName B- -PINATTR SpiceOrder 2 -PIN 80 48 NONE 0 -PINATTR PinName Y- -PINATTR SpiceOrder 3 -PIN -64 32 NONE 8 -PINATTR PinName A- -PINATTR SpiceOrder 4 -PIN -64 96 NONE 8 -PINATTR PinName B+ -PINATTR SpiceOrder 5 -PIN 80 80 NONE 8 -PINATTR PinName Y+ -PINATTR SpiceOrder 6 +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +LINE Normal -48 32 -48 48 +LINE Normal -64 32 -48 32 +LINE Normal -64 48 -48 48 +LINE Normal -48 96 -48 80 +LINE Normal -64 96 -48 96 +LINE Normal -64 80 -48 80 +LINE Normal 64 48 64 64 +LINE Normal 80 48 64 48 +LINE Normal 80 80 64 80 +LINE Normal 64 80 64 64 +TEXT 1 48 Center 0 XOR +SYMATTR Description XOR gate +PIN -64 48 NONE 0 +PINATTR PinName A+ +PINATTR SpiceOrder 1 +PIN -64 80 NONE 0 +PINATTR PinName B- +PINATTR SpiceOrder 2 +PIN 80 48 NONE 0 +PINATTR PinName Y- +PINATTR SpiceOrder 3 +PIN -64 32 NONE 8 +PINATTR PinName A- +PINATTR SpiceOrder 4 +PIN -64 96 NONE 8 +PINATTR PinName B+ +PINATTR SpiceOrder 5 +PIN 80 80 NONE 8 +PINATTR PinName Y+ +PINATTR SpiceOrder 6 -- cgit