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Version 4
SHEET 1 880 680
WIRE 32 144 16 144
WIRE 272 160 256 160
WIRE 32 176 16 176
FLAG 16 144 A
IOPIN 16 144 In
FLAG 16 176 B
IOPIN 16 176 In
FLAG 272 160 Y
IOPIN 272 160 Out
SYMBOL ternary-logic\\CMOS\\2_input_inverting_consensus 80 96 R0
SYMATTR InstName U1
SYMBOL ternary-logic\\CMOS\\standard_inverter 192 112 R0
SYMATTR InstName U2
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