diff options
| author | Jed Barber <jjbarber@y7mail.com> | 2014-02-26 22:30:51 +1100 |
|---|---|---|
| committer | Jed Barber <jjbarber@y7mail.com> | 2014-02-26 22:30:51 +1100 |
| commit | 029d0d8e09e56ee12c98475d4e98e6388f977922 (patch) | |
| tree | e1992b15ab6b0da1291711444b02b4e287787423 | |
| parent | 050a580d1d04a4f077f416023581ba4d7cb1f327 (diff) | |
Added symbols (copies of the CMOS symbols)
| -rw-r--r-- | RMOS/antimax.asy | 24 | ||||
| -rw-r--r-- | RMOS/antimin.asy | 24 | ||||
| -rw-r--r-- | RMOS/buffer.asy | 17 | ||||
| -rw-r--r-- | RMOS/clamp_down.asy | 20 | ||||
| -rw-r--r-- | RMOS/clamp_up.asy | 20 | ||||
| -rw-r--r-- | RMOS/consensus.asy | 22 | ||||
| -rw-r--r-- | RMOS/decrement.asy | 17 | ||||
| -rw-r--r-- | RMOS/equality.asy | 22 | ||||
| -rw-r--r-- | RMOS/gullible.asy | 22 | ||||
| -rw-r--r-- | RMOS/increment.asy | 17 | ||||
| -rw-r--r-- | RMOS/inverting_consensus.asy | 23 | ||||
| -rw-r--r-- | RMOS/inverting_gullible.asy | 23 | ||||
| -rw-r--r-- | RMOS/is_false.asy | 17 | ||||
| -rw-r--r-- | RMOS/is_true.asy | 17 | ||||
| -rw-r--r-- | RMOS/is_unknown.asy | 17 | ||||
| -rw-r--r-- | RMOS/max.asy | 22 | ||||
| -rw-r--r-- | RMOS/min.asy | 22 | ||||
| -rw-r--r-- | RMOS/monadic_decoder.asy | 28 | ||||
| -rw-r--r-- | RMOS/negative_threshold_inverter.asy | 18 | ||||
| -rw-r--r-- | RMOS/positive_threshold_inverter.asy | 18 | ||||
| -rw-r--r-- | RMOS/standard_inverter.asy | 18 | ||||
| -rw-r--r-- | RMOS/sum.asy | 22 | ||||
| -rw-r--r-- | RMOS/xor.asy | 22 |
23 files changed, 472 insertions, 0 deletions
diff --git a/RMOS/antimax.asy b/RMOS/antimax.asy new file mode 100644 index 0000000..e29234c --- /dev/null +++ b/RMOS/antimax.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 77 Center 0 MAX +TEXT 0 52 Center 0 ANTI +SYMATTR Description 2-input ANTIMAX gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/antimin.asy b/RMOS/antimin.asy new file mode 100644 index 0000000..1b33509 --- /dev/null +++ b/RMOS/antimin.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 77 Center 0 MIN +TEXT 0 52 Center 0 ANTI +SYMATTR Description 2-input ANTIMIN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/buffer.asy b/RMOS/buffer.asy new file mode 100644 index 0000000..e92d13d --- /dev/null +++ b/RMOS/buffer.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 BUF +SYMATTR Description Buffer +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/clamp_down.asy b/RMOS/clamp_down.asy new file mode 100644 index 0000000..3fccbd7 --- /dev/null +++ b/RMOS/clamp_down.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MIN +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP DOWN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/clamp_up.asy b/RMOS/clamp_up.asy new file mode 100644 index 0000000..b4ebc93 --- /dev/null +++ b/RMOS/clamp_up.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MAX +TEXT -63 80 Left 0 0 +SYMATTR Description CLAMP UP gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/consensus.asy b/RMOS/consensus.asy new file mode 100644 index 0000000..1201fa4 --- /dev/null +++ b/RMOS/consensus.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 CON +SYMATTR Description 2-input consensus gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/decrement.asy b/RMOS/decrement.asy new file mode 100644 index 0000000..3e3d8f7 --- /dev/null +++ b/RMOS/decrement.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 -1 +SYMATTR Description Decrement gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/equality.asy b/RMOS/equality.asy new file mode 100644 index 0000000..c6470ce --- /dev/null +++ b/RMOS/equality.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 = +SYMATTR Description 2-input equality gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/gullible.asy b/RMOS/gullible.asy new file mode 100644 index 0000000..cd75b7e --- /dev/null +++ b/RMOS/gullible.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 GUL +SYMATTR Description 2-input gullible gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/increment.asy b/RMOS/increment.asy new file mode 100644 index 0000000..b4f6f39 --- /dev/null +++ b/RMOS/increment.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 +1 +SYMATTR Description Increment gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/inverting_consensus.asy b/RMOS/inverting_consensus.asy new file mode 100644 index 0000000..c0f87df --- /dev/null +++ b/RMOS/inverting_consensus.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 CON +SYMATTR Description 2-input inverting consensus +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/inverting_gullible.asy b/RMOS/inverting_gullible.asy new file mode 100644 index 0000000..3e6991f --- /dev/null +++ b/RMOS/inverting_gullible.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 56 48 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 0 52 Center 0 GUL +SYMATTR Description 2-input inverting gullible +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/is_false.asy b/RMOS/is_false.asy new file mode 100644 index 0000000..e5e3fee --- /dev/null +++ b/RMOS/is_false.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =- +SYMATTR Description IS FALSE gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/is_true.asy b/RMOS/is_true.asy new file mode 100644 index 0000000..5105d90 --- /dev/null +++ b/RMOS/is_true.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =+ +SYMATTR Description IS TRUE gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/is_unknown.asy b/RMOS/is_unknown.asy new file mode 100644 index 0000000..8ffb820 --- /dev/null +++ b/RMOS/is_unknown.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +TEXT 0 48 Center 0 =0 +SYMATTR Description IS UNKNOWN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/max.asy b/RMOS/max.asy new file mode 100644 index 0000000..5552b62 --- /dev/null +++ b/RMOS/max.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MAX +SYMATTR Description 2-input MAX gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/min.asy b/RMOS/min.asy new file mode 100644 index 0000000..0efa86d --- /dev/null +++ b/RMOS/min.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 MIN +SYMATTR Description 2-input MIN gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/monadic_decoder.asy b/RMOS/monadic_decoder.asy new file mode 100644 index 0000000..7e2d830 --- /dev/null +++ b/RMOS/monadic_decoder.asy @@ -0,0 +1,28 @@ +Version 4 +SymbolType CELL +LINE Normal 64 80 32 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 128 32 32 +LINE Normal -32 128 32 128 +LINE Normal -32 32 -32 128 +LINE Normal 64 48 32 48 +LINE Normal 64 112 32 112 +LINE Normal -64 80 -32 80 +TEXT -20 80 Left 0 = +TEXT 3 46 Left 0 - +TEXT 9 46 Left 0 - +TEXT 10 80 Center 0 0 +TEXT 10 112 Center 0 + +SYMATTR Description Monadic decoder gate +PIN -64 80 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 8 +PINATTR PinName Y1 +PINATTR SpiceOrder 2 +PIN 64 80 NONE 8 +PINATTR PinName Y2 +PINATTR SpiceOrder 3 +PIN 64 112 NONE 8 +PINATTR PinName Y3 +PINATTR SpiceOrder 4 diff --git a/RMOS/negative_threshold_inverter.asy b/RMOS/negative_threshold_inverter.asy new file mode 100644 index 0000000..91e3aad --- /dev/null +++ b/RMOS/negative_threshold_inverter.asy @@ -0,0 +1,18 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 NTI +SYMATTR Description Negative threshold inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/positive_threshold_inverter.asy b/RMOS/positive_threshold_inverter.asy new file mode 100644 index 0000000..1122cb4 --- /dev/null +++ b/RMOS/positive_threshold_inverter.asy @@ -0,0 +1,18 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 PTI +SYMATTR Description Positive threshold inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/standard_inverter.asy b/RMOS/standard_inverter.asy new file mode 100644 index 0000000..fe479d7 --- /dev/null +++ b/RMOS/standard_inverter.asy @@ -0,0 +1,18 @@ +Version 4 +SymbolType CELL +LINE Normal 32 48 64 48 +LINE Normal -32 48 -48 48 +LINE Normal 32 32 -32 32 +LINE Normal 32 64 32 32 +LINE Normal -32 64 32 64 +LINE Normal -32 32 -32 64 +LINE Normal 32 40 32 48 +LINE Normal 47 48 32 40 +TEXT 0 48 Center 0 NEG +SYMATTR Description Inverter +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 64 48 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 2 diff --git a/RMOS/sum.asy b/RMOS/sum.asy new file mode 100644 index 0000000..3ad5226 --- /dev/null +++ b/RMOS/sum.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 SUM +SYMATTR Description SUM gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 diff --git a/RMOS/xor.asy b/RMOS/xor.asy new file mode 100644 index 0000000..bdf30a2 --- /dev/null +++ b/RMOS/xor.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 32 64 +LINE Normal 32 64 32 56 +LINE Normal 64 64 48 64 +LINE Normal -32 48 -48 48 +LINE Normal -32 80 -48 80 +LINE Normal 32 32 -32 32 +LINE Normal 32 96 32 32 +LINE Normal -32 96 32 96 +LINE Normal -32 32 -32 96 +TEXT 1 48 Center 0 XOR +SYMATTR Description XOR gate +PIN -48 48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -48 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Y +PINATTR SpiceOrder 3 |