Constructed simulated ternary 2 input MIN gate

1 files changed, 35 insertions, 0 deletions

diff --git a/simulated/2_input_min.asc b/simulated/2_input_min.asc
new file mode 100644
index 0000000..987253e
--- /dev/null
+++ b/simulated/2_input_min.asc
@@ -0,0 +1,35 @@
+Version 4
+SHEET 1 880 680
+WIRE 144 16 -32 16
+WIRE 320 32 208 32
+WIRE 64 80 -32 80
+WIRE 144 80 96 80
+WIRE 160 96 160 80
+WIRE 96 144 96 80
+WIRE 96 144 32 144
+WIRE 32 208 32 144
+WIRE 32 208 -32 208
+WIRE 64 208 64 80
+WIRE 144 208 64 208
+WIRE 320 224 208 224
+WIRE 144 272 -32 272
+WIRE 160 288 160 272
+FLAG -32 16 A-
+IOPIN -32 16 In
+FLAG -32 80 A+
+IOPIN -32 80 In
+FLAG -32 208 B-
+IOPIN -32 208 In
+FLAG -32 272 B+
+IOPIN -32 272 In
+FLAG 160 96 0
+FLAG 160 288 0
+FLAG 320 32 Y-
+IOPIN 320 32 Out
+FLAG 320 224 Y+
+IOPIN 320 224 Out
+SYMBOL Digital\\or 176 -16 R0
+SYMATTR InstName A1
+SYMBOL Digital\\and 176 176 R0
+SYMATTR InstName A2
+TEXT 248 312 Left 0 ;Total = 12 transistors