Made symbols for all simulated ternary gates so far

8 files changed, 256 insertions, 0 deletions

diff --git a/simulated/decrement.asy b/simulated/decrement.asy
new file mode 100644
index 0000000..d3249e6
--- /dev/null
+++ b/simulated/decrement.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 -1
+SYMATTR Description DECREMENT gate
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/increment.asy b/simulated/increment.asy
new file mode 100644
index 0000000..a835e77
--- /dev/null
+++ b/simulated/increment.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 +1
+SYMATTR Description INCREMENT gate
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/is_false.asy b/simulated/is_false.asy
new file mode 100644
index 0000000..aa91398
--- /dev/null
+++ b/simulated/is_false.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 =-
+SYMATTR Description IS FALSE gate
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/is_true.asy b/simulated/is_true.asy
new file mode 100644
index 0000000..1a1203c
--- /dev/null
+++ b/simulated/is_true.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 =+
+SYMATTR Description IS TRUE gate
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/is_unknown.asy b/simulated/is_unknown.asy
new file mode 100644
index 0000000..952a28a
--- /dev/null
+++ b/simulated/is_unknown.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 =0
+SYMATTR Description IS UNKNOWN gate
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/negative_threshold_inverter.asy b/simulated/negative_threshold_inverter.asy
new file mode 100644
index 0000000..88aa7bd
--- /dev/null
+++ b/simulated/negative_threshold_inverter.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 NTI
+SYMATTR Description Negative threshold inverter
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/positive_threshold_inverter.asy b/simulated/positive_threshold_inverter.asy
new file mode 100644
index 0000000..a180db8
--- /dev/null
+++ b/simulated/positive_threshold_inverter.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 PTI
+SYMATTR Description Positive threshold inverter
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/standard_inverter.asy b/simulated/standard_inverter.asy
new file mode 100644
index 0000000..4a10402
--- /dev/null
+++ b/simulated/standard_inverter.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 NEG
+SYMATTR Description Inverter
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4