Added gullible and inverting gullible gates

4 files changed, 224 insertions, 0 deletions

diff --git a/CMOS/gullible.asc b/CMOS/gullible.asc
new file mode 100644
index 0000000..ab6240d
--- /dev/null
+++ b/CMOS/gullible.asc
@@ -0,0 +1,15 @@
+Version 4
+SHEET 1 880 680
+WIRE 0 144 -16 144
+WIRE 240 160 224 160
+WIRE 0 176 -16 176
+FLAG -16 144 A
+IOPIN -16 144 In
+FLAG -16 176 B
+IOPIN -16 176 In
+FLAG 240 160 Y
+IOPIN 240 160 Out
+SYMBOL .\\inverting_gullible 48 96 R0
+SYMATTR InstName U1
+SYMBOL .\\standard_inverter 160 112 R0
+SYMATTR InstName U2
diff --git a/CMOS/gullible.asy b/CMOS/gullible.asy
new file mode 100644
index 0000000..d69c87a
--- /dev/null
+++ b/CMOS/gullible.asy
@@ -0,0 +1,23 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 0 52 Center 0 GUL
+SYMATTR Description 2-input gullible gate
+SYMATTR Prefix X
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/inverting_gullible.asc b/CMOS/inverting_gullible.asc
new file mode 100644
index 0000000..8a4888c
--- /dev/null
+++ b/CMOS/inverting_gullible.asc
@@ -0,0 +1,162 @@
+Version 4
+SHEET 1 1168 708
+WIRE -352 -208 -384 -208
+WIRE -80 -208 -272 -208
+WIRE 176 -208 -80 -208
+WIRE -384 -176 -384 -208
+WIRE 464 -160 288 -160
+WIRE 720 -160 464 -160
+WIRE 976 -160 720 -160
+WIRE 1088 -160 976 -160
+WIRE -80 -144 -80 -208
+WIRE 176 -144 176 -208
+WIRE -176 -128 -240 -128
+WIRE -128 -128 -176 -128
+WIRE 128 -128 80 -128
+WIRE 464 -80 464 -160
+WIRE 720 -80 720 -160
+WIRE 976 -80 976 -160
+WIRE -176 -32 -176 -128
+WIRE 80 -32 80 -128
+WIRE 80 -32 -176 -32
+WIRE 336 -32 80 -32
+WIRE 416 0 384 0
+WIRE 672 0 624 0
+WIRE 928 0 816 0
+WIRE 32 32 -176 32
+WIRE 384 32 384 0
+WIRE 384 32 32 32
+WIRE 624 32 624 0
+WIRE 624 32 384 32
+WIRE 880 32 624 32
+WIRE -80 48 -80 -48
+WIRE 176 48 176 -48
+WIRE -176 64 -176 32
+WIRE -176 64 -352 64
+WIRE -128 64 -176 64
+WIRE 32 64 32 32
+WIRE 128 64 32 64
+WIRE 336 96 336 -32
+WIRE 624 96 336 96
+WIRE 816 96 816 0
+WIRE 816 96 624 96
+WIRE 464 112 464 16
+WIRE 720 112 720 16
+WIRE 976 112 976 16
+WIRE 384 192 384 32
+WIRE 416 192 384 192
+WIRE 624 192 624 96
+WIRE 672 192 624 192
+WIRE 880 192 880 32
+WIRE 928 192 880 192
+WIRE -80 208 -80 144
+WIRE 176 208 176 144
+WIRE 176 208 -80 208
+WIRE 288 208 288 -160
+WIRE 288 208 176 208
+WIRE -80 272 -80 208
+WIRE 176 272 176 208
+WIRE 720 272 720 208
+WIRE 976 272 976 208
+WIRE 976 272 720 272
+WIRE 464 304 464 208
+WIRE 976 336 976 272
+WIRE -240 352 -240 -128
+WIRE -240 352 -352 352
+WIRE -128 352 -240 352
+WIRE 128 352 80 352
+WIRE 336 384 336 96
+WIRE 416 384 336 384
+WIRE -240 400 -240 352
+WIRE 80 400 80 352
+WIRE 80 400 -240 400
+WIRE -80 464 -80 368
+WIRE 176 464 176 368
+WIRE 464 496 464 400
+WIRE -176 544 -176 64
+WIRE -128 544 -176 544
+WIRE 32 544 32 64
+WIRE 128 544 32 544
+WIRE 336 576 336 384
+WIRE 416 576 336 576
+WIRE -352 624 -384 624
+WIRE -80 624 -80 560
+WIRE -80 624 -272 624
+WIRE 176 624 176 560
+WIRE 176 624 -80 624
+WIRE 464 624 464 592
+WIRE 720 624 720 272
+WIRE 720 624 464 624
+WIRE -384 656 -384 624
+FLAG -384 656 0
+FLAG 976 336 0
+FLAG -384 -176 0
+FLAG -352 64 A
+IOPIN -352 64 In
+FLAG -352 352 B
+IOPIN -352 352 In
+FLAG 1088 -160 Y
+IOPIN 1088 -160 Out
+SYMBOL pmos -128 -48 M180
+SYMATTR InstName M1
+SYMATTR Value P-ENH
+SYMBOL pmos -128 144 M180
+SYMATTR InstName M2
+SYMATTR Value P-ELOW
+SYMBOL pmos 128 -48 M180
+SYMATTR InstName M3
+SYMATTR Value P-ELOW
+SYMBOL pmos 128 144 M180
+SYMATTR InstName M4
+SYMATTR Value P-ENH
+SYMBOL nmos -128 272 R0
+SYMATTR InstName M5
+SYMATTR Value N-ELOW
+SYMBOL nmos -128 464 R0
+SYMATTR InstName M6
+SYMATTR Value N-ENH
+SYMBOL nmos 128 272 R0
+SYMATTR InstName M7
+SYMATTR Value N-ENH
+SYMBOL nmos 128 464 R0
+SYMATTR InstName M8
+SYMATTR Value N-ELOW
+SYMBOL voltage -256 -208 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -256 624 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value -1
+SYMBOL nmos 416 -80 R0
+SYMATTR InstName M9
+SYMATTR Value N-DLOW
+SYMBOL nmos 672 -80 R0
+SYMATTR InstName M10
+SYMATTR Value N-ELOW
+SYMBOL nmos 928 -80 R0
+SYMATTR InstName M11
+SYMATTR Value N-ELOW
+SYMBOL pmos 416 112 R0
+SYMATTR InstName M12
+SYMATTR Value P-DLOW
+SYMBOL pmos 672 112 R0
+SYMATTR InstName M13
+SYMATTR Value P-ELOW
+SYMBOL pmos 928 112 R0
+SYMATTR InstName M14
+SYMATTR Value P-ELOW
+SYMBOL nmos 416 304 R0
+SYMATTR InstName M15
+SYMATTR Value N-DLOW
+SYMBOL pmos 416 496 R0
+SYMATTR InstName M16
+SYMATTR Value P-DLOW
+TEXT 280 -272 Left 0 !.inc ./custom.mos
diff --git a/CMOS/inverting_gullible.asy b/CMOS/inverting_gullible.asy
new file mode 100644
index 0000000..29e63f1
--- /dev/null
+++ b/CMOS/inverting_gullible.asy
@@ -0,0 +1,24 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 56 48 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 0 52 Center 0 GUL
+SYMATTR Description 2-input inverting gullible
+SYMATTR Prefix X
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3