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authorJed Barber <jjbarber@y7mail.com>2014-02-14 00:57:24 +1100
committerJed Barber <jjbarber@y7mail.com>2014-02-14 00:57:24 +1100
commit779850bf1cb8b3bc2156f594c29a0cb3a65cd03a (patch)
tree974e637496c1156180559e342d37d4cb97821210
parenteaa9f4d86ab2a7b346b0ed9f1e474ba19e23597f (diff)
Constructed simulated ternary SUM gate
-rw-r--r--simulated/sum.asc94
1 files changed, 94 insertions, 0 deletions
diff --git a/simulated/sum.asc b/simulated/sum.asc
new file mode 100644
index 0000000..f2c90c1
--- /dev/null
+++ b/simulated/sum.asc
@@ -0,0 +1,94 @@
+Version 4
+SHEET 1 880 680
+WIRE 160 -224 -176 -224
+WIRE 320 -176 224 -176
+WIRE 160 -160 -144 -160
+WIRE 160 -96 -112 -96
+WIRE 112 -64 -80 -64
+WIRE 288 -48 224 -48
+WIRE 160 -32 80 -32
+WIRE -112 32 -112 -96
+WIRE -112 32 -256 32
+WIRE -32 32 -112 32
+WIRE 112 32 112 -64
+WIRE 160 32 112 32
+WIRE 320 32 320 -176
+WIRE 352 32 320 32
+WIRE 288 64 288 -48
+WIRE 352 64 288 64
+WIRE 112 80 32 80
+WIRE 256 80 224 80
+WIRE 528 80 416 80
+WIRE -144 96 -144 -160
+WIRE -144 96 -256 96
+WIRE -32 96 -144 96
+WIRE 112 96 112 80
+WIRE 160 96 112 96
+WIRE 256 96 256 80
+WIRE 352 96 256 96
+WIRE -80 176 -80 -64
+WIRE -80 176 -256 176
+WIRE -32 176 -80 176
+WIRE 112 176 112 96
+WIRE 160 176 112 176
+WIRE 352 176 256 176
+WIRE 352 208 288 208
+WIRE 80 224 80 -32
+WIRE 80 224 32 224
+WIRE 256 224 256 176
+WIRE 256 224 224 224
+WIRE 528 224 416 224
+WIRE -208 240 -256 240
+WIRE -176 240 -176 -224
+WIRE -176 240 -208 240
+WIRE -32 240 -176 240
+WIRE 160 240 112 240
+WIRE 352 240 320 240
+WIRE 80 304 80 224
+WIRE 160 304 80 304
+WIRE -208 336 -208 240
+WIRE 112 336 112 240
+WIRE 112 336 -208 336
+WIRE 288 352 288 208
+WIRE 288 352 224 352
+WIRE -144 368 -144 96
+WIRE 160 368 -144 368
+WIRE -112 432 -112 32
+WIRE 160 432 -112 432
+WIRE 320 480 320 240
+WIRE 320 480 224 480
+WIRE -80 496 -80 176
+WIRE 160 496 -80 496
+FLAG 528 80 Y-
+IOPIN 528 80 Out
+FLAG 528 224 Y+
+IOPIN 528 224 Out
+FLAG -256 32 A-
+IOPIN -256 32 In
+FLAG -256 96 A+
+IOPIN -256 96 In
+FLAG -256 176 B-
+IOPIN -256 176 In
+FLAG -256 240 B+
+IOPIN -256 240 In
+SYMBOL Digital\\or 0 0 R0
+SYMATTR InstName A1
+SYMBOL Digital\\or 0 144 R0
+SYMATTR InstName A2
+SYMBOL Digital\\and 192 0 R0
+SYMATTR InstName A3
+SYMBOL Digital\\and 192 144 R0
+SYMATTR InstName A4
+SYMBOL Digital\\and 192 -128 R0
+SYMATTR InstName A5
+SYMBOL Digital\\and 192 -256 R0
+SYMATTR InstName A6
+SYMBOL Digital\\and 192 272 R0
+SYMATTR InstName A7
+SYMBOL Digital\\and 192 400 R0
+SYMATTR InstName A8
+SYMBOL Digital\\and 384 144 R0
+SYMATTR InstName A9
+SYMBOL Digital\\and 384 0 R0
+SYMATTR InstName A10
+TEXT 408 328 Left 0 ;Total = 52 transistors