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authorJed Barber <jjbarber@y7mail.com>2014-01-31 00:00:21 +1100
committerJed Barber <jjbarber@y7mail.com>2014-01-31 00:00:21 +1100
commit2dfca24fd2ddf2bb489ada5022810ba5c204284e (patch)
tree2f654b06c393ce6e89f6eb530120270e3fda469e /CMOS
parent7833a8421b1a69c590b437823f4a2d841c31c91e (diff)
Fixed attribute problem to allow component usage in other circuits
Diffstat (limited to 'CMOS')
-rw-r--r--CMOS/2_input_antimax.asy1
-rw-r--r--CMOS/2_input_antimin.asy1
-rw-r--r--CMOS/2_input_max.asy1
-rw-r--r--CMOS/2_input_min.asy1
-rw-r--r--CMOS/buffer.asy1
-rw-r--r--CMOS/clamp_down.asy1
-rw-r--r--CMOS/clamp_up.asy1
-rw-r--r--CMOS/consensus.asy1
-rw-r--r--CMOS/decrement.asy1
-rw-r--r--CMOS/gullible.asy1
-rw-r--r--CMOS/increment.asy1
-rw-r--r--CMOS/inverting_consensus.asy1
-rw-r--r--CMOS/inverting_gullible.asy1
-rw-r--r--CMOS/is_false.asy1
-rw-r--r--CMOS/is_true.asy1
-rw-r--r--CMOS/is_unknown.asy1
-rw-r--r--CMOS/monadic_decoder.asy1
-rw-r--r--CMOS/negative_threshold_inverter.asy1
-rw-r--r--CMOS/positive_threshold_inverter.asy1
-rw-r--r--CMOS/standard_inverter.asy1
20 files changed, 0 insertions, 20 deletions
diff --git a/CMOS/2_input_antimax.asy b/CMOS/2_input_antimax.asy
index 768c42a..e29234c 100644
--- a/CMOS/2_input_antimax.asy
+++ b/CMOS/2_input_antimax.asy
@@ -13,7 +13,6 @@ LINE Normal -32 32 -32 96
TEXT 0 77 Center 0 MAX
TEXT 0 52 Center 0 ANTI
SYMATTR Description 2-input ANTIMAX gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_antimin.asy b/CMOS/2_input_antimin.asy
index db357ec..1b33509 100644
--- a/CMOS/2_input_antimin.asy
+++ b/CMOS/2_input_antimin.asy
@@ -13,7 +13,6 @@ LINE Normal -32 32 -32 96
TEXT 0 77 Center 0 MIN
TEXT 0 52 Center 0 ANTI
SYMATTR Description 2-input ANTIMIN gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_max.asy b/CMOS/2_input_max.asy
index 4470927..5552b62 100644
--- a/CMOS/2_input_max.asy
+++ b/CMOS/2_input_max.asy
@@ -11,7 +11,6 @@ LINE Normal -32 96 32 96
LINE Normal -32 32 -32 96
TEXT 1 48 Center 0 MAX
SYMATTR Description 2-input MAX gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_min.asy b/CMOS/2_input_min.asy
index df47c15..0efa86d 100644
--- a/CMOS/2_input_min.asy
+++ b/CMOS/2_input_min.asy
@@ -11,7 +11,6 @@ LINE Normal -32 96 32 96
LINE Normal -32 32 -32 96
TEXT 1 48 Center 0 MIN
SYMATTR Description 2-input MIN gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/buffer.asy b/CMOS/buffer.asy
index 35ccb12..e92d13d 100644
--- a/CMOS/buffer.asy
+++ b/CMOS/buffer.asy
@@ -8,7 +8,6 @@ LINE Normal -32 64 32 64
LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
TEXT 0 48 Center 0 BUF
-SYMATTR Prefix X
SYMATTR Description Buffer
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/clamp_down.asy b/CMOS/clamp_down.asy
index 8888ac4..3fccbd7 100644
--- a/CMOS/clamp_down.asy
+++ b/CMOS/clamp_down.asy
@@ -12,7 +12,6 @@ LINE Normal -32 32 -32 96
TEXT 1 48 Center 0 MIN
TEXT -63 80 Left 0 0
SYMATTR Description CLAMP DOWN gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/clamp_up.asy b/CMOS/clamp_up.asy
index adcf7d9..b4ebc93 100644
--- a/CMOS/clamp_up.asy
+++ b/CMOS/clamp_up.asy
@@ -12,7 +12,6 @@ LINE Normal -32 32 -32 96
TEXT 1 48 Center 0 MAX
TEXT -63 80 Left 0 0
SYMATTR Description CLAMP UP gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/consensus.asy b/CMOS/consensus.asy
index 4604eb5..1201fa4 100644
--- a/CMOS/consensus.asy
+++ b/CMOS/consensus.asy
@@ -11,7 +11,6 @@ LINE Normal -32 96 32 96
LINE Normal -32 32 -32 96
TEXT 0 52 Center 0 CON
SYMATTR Description 2-input consensus gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/decrement.asy b/CMOS/decrement.asy
index c178fc5..3e3d8f7 100644
--- a/CMOS/decrement.asy
+++ b/CMOS/decrement.asy
@@ -8,7 +8,6 @@ LINE Normal -32 64 32 64
LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
TEXT 0 48 Center 0 -1
-SYMATTR Prefix X
SYMATTR Description Decrement gate
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/gullible.asy b/CMOS/gullible.asy
index d69c87a..cd75b7e 100644
--- a/CMOS/gullible.asy
+++ b/CMOS/gullible.asy
@@ -11,7 +11,6 @@ LINE Normal -32 96 32 96
LINE Normal -32 32 -32 96
TEXT 0 52 Center 0 GUL
SYMATTR Description 2-input gullible gate
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/increment.asy b/CMOS/increment.asy
index c7a2b36..b4f6f39 100644
--- a/CMOS/increment.asy
+++ b/CMOS/increment.asy
@@ -8,7 +8,6 @@ LINE Normal -32 64 32 64
LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
TEXT 0 48 Center 0 +1
-SYMATTR Prefix X
SYMATTR Description Increment gate
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/inverting_consensus.asy b/CMOS/inverting_consensus.asy
index f6cc640..c0f87df 100644
--- a/CMOS/inverting_consensus.asy
+++ b/CMOS/inverting_consensus.asy
@@ -12,7 +12,6 @@ LINE Normal -32 96 32 96
LINE Normal -32 32 -32 96
TEXT 0 52 Center 0 CON
SYMATTR Description 2-input inverting consensus
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/inverting_gullible.asy b/CMOS/inverting_gullible.asy
index 29e63f1..3e6991f 100644
--- a/CMOS/inverting_gullible.asy
+++ b/CMOS/inverting_gullible.asy
@@ -12,7 +12,6 @@ LINE Normal -32 96 32 96
LINE Normal -32 32 -32 96
TEXT 0 52 Center 0 GUL
SYMATTR Description 2-input inverting gullible
-SYMATTR Prefix X
PIN -48 48 NONE 0
PINATTR PinName A
PINATTR SpiceOrder 1
diff --git a/CMOS/is_false.asy b/CMOS/is_false.asy
index 6c8c5a2..e5e3fee 100644
--- a/CMOS/is_false.asy
+++ b/CMOS/is_false.asy
@@ -8,7 +8,6 @@ LINE Normal -32 64 32 64
LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
TEXT 0 48 Center 0 =-
-SYMATTR Prefix X
SYMATTR Description IS FALSE gate
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/is_true.asy b/CMOS/is_true.asy
index 42c7c1b..5105d90 100644
--- a/CMOS/is_true.asy
+++ b/CMOS/is_true.asy
@@ -8,7 +8,6 @@ LINE Normal -32 64 32 64
LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
TEXT 0 48 Center 0 =+
-SYMATTR Prefix X
SYMATTR Description IS TRUE gate
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/is_unknown.asy b/CMOS/is_unknown.asy
index 94fa3b7..8ffb820 100644
--- a/CMOS/is_unknown.asy
+++ b/CMOS/is_unknown.asy
@@ -8,7 +8,6 @@ LINE Normal -32 64 32 64
LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
TEXT 0 48 Center 0 =0
-SYMATTR Prefix X
SYMATTR Description IS UNKNOWN gate
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/monadic_decoder.asy b/CMOS/monadic_decoder.asy
index d3c4a72..7e2d830 100644
--- a/CMOS/monadic_decoder.asy
+++ b/CMOS/monadic_decoder.asy
@@ -13,7 +13,6 @@ TEXT 3 46 Left 0 -
TEXT 9 46 Left 0 -
TEXT 10 80 Center 0 0
TEXT 10 112 Center 0 +
-SYMATTR Prefix X
SYMATTR Description Monadic decoder gate
PIN -64 80 NONE 8
PINATTR PinName A
diff --git a/CMOS/negative_threshold_inverter.asy b/CMOS/negative_threshold_inverter.asy
index d285f5c..91e3aad 100644
--- a/CMOS/negative_threshold_inverter.asy
+++ b/CMOS/negative_threshold_inverter.asy
@@ -9,7 +9,6 @@ LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
LINE Normal 47 48 32 40
TEXT 0 48 Center 0 NTI
-SYMATTR Prefix X
SYMATTR Description Negative threshold inverter
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/positive_threshold_inverter.asy b/CMOS/positive_threshold_inverter.asy
index cea7fec..1122cb4 100644
--- a/CMOS/positive_threshold_inverter.asy
+++ b/CMOS/positive_threshold_inverter.asy
@@ -9,7 +9,6 @@ LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
LINE Normal 47 48 32 40
TEXT 0 48 Center 0 PTI
-SYMATTR Prefix X
SYMATTR Description Positive threshold inverter
PIN -48 48 NONE 0
PINATTR PinName A
diff --git a/CMOS/standard_inverter.asy b/CMOS/standard_inverter.asy
index db5b740..fe479d7 100644
--- a/CMOS/standard_inverter.asy
+++ b/CMOS/standard_inverter.asy
@@ -9,7 +9,6 @@ LINE Normal -32 32 -32 64
LINE Normal 32 40 32 48
LINE Normal 47 48 32 40
TEXT 0 48 Center 0 NEG
-SYMATTR Prefix X
SYMATTR Description Inverter
PIN -48 48 NONE 0
PINATTR PinName A