diff options
| author | Jed Barber <jjbarber@y7mail.com> | 2014-01-28 02:18:06 +1100 |
|---|---|---|
| committer | Jed Barber <jjbarber@y7mail.com> | 2014-01-28 02:18:06 +1100 |
| commit | cd6b654eeacfb033f1977b81ad1f152ec040cca2 (patch) | |
| tree | b41913c61a834eea2bc0928923635f1cc8771d04 /RMOS | |
Circuits already constructed
Diffstat (limited to 'RMOS')
| -rw-r--r-- | RMOS/antimin.asc | 88 | ||||
| -rw-r--r-- | RMOS/standard_inverter.asc | 58 |
2 files changed, 146 insertions, 0 deletions
diff --git a/RMOS/antimin.asc b/RMOS/antimin.asc new file mode 100644 index 0000000..28e5cd4 --- /dev/null +++ b/RMOS/antimin.asc @@ -0,0 +1,88 @@ +Version 4 +SHEET 1 880 680 +WIRE -320 -176 -400 -176 +WIRE -96 -176 -240 -176 +WIRE 176 -176 -96 -176 +WIRE -96 -144 -96 -176 +WIRE 176 -144 176 -176 +WIRE -144 -128 -176 -128 +WIRE 128 -128 48 -128 +WIRE 48 -48 48 -128 +WIRE 48 -48 -32 -48 +WIRE -96 -16 -96 -48 +WIRE 48 -16 -96 -16 +WIRE 176 -16 176 -48 +WIRE 176 -16 48 -16 +WIRE 48 16 48 -16 +WIRE -400 48 -400 -176 +WIRE -320 48 -400 48 +WIRE -176 48 -176 -128 +WIRE -176 48 -240 48 +WIRE -400 112 -400 48 +WIRE -400 112 -480 112 +WIRE 48 112 48 96 +WIRE 272 112 48 112 +WIRE 48 128 48 112 +WIRE -480 144 -480 112 +WIRE -400 192 -400 112 +WIRE -320 192 -400 192 +WIRE -32 192 -32 -48 +WIRE -32 192 -240 192 +WIRE 48 240 48 208 +WIRE -32 320 -32 192 +WIRE 0 320 -32 320 +WIRE 48 368 48 336 +WIRE -176 448 -176 48 +WIRE 0 448 -176 448 +WIRE -400 496 -400 192 +WIRE -320 496 -400 496 +WIRE 48 496 48 464 +WIRE 48 496 -240 496 +FLAG -480 144 0 +SYMBOL pmos -144 -48 M180 +SYMATTR InstName M1 +SYMATTR Value AO6407 +SYMBOL pmos 128 -48 M180 +SYMATTR InstName M2 +SYMATTR Value AO6407 +SYMBOL nmos 0 240 R0 +SYMATTR InstName M3 +SYMATTR Value AO6408 +SYMBOL nmos 0 368 R0 +SYMATTR InstName M4 +SYMATTR Value AO6408 +SYMBOL res 32 112 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL res 32 0 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +SYMBOL voltage -224 -176 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 2 +SYMBOL voltage -224 48 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value SINE(0 2 2) +SYMBOL voltage -224 192 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value SINE(0 2 2 0.1) +SYMBOL voltage -224 496 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value -2 +TEXT -500 562 Left 0 !.tran 1 diff --git a/RMOS/standard_inverter.asc b/RMOS/standard_inverter.asc new file mode 100644 index 0000000..ba1bbc3 --- /dev/null +++ b/RMOS/standard_inverter.asc @@ -0,0 +1,58 @@ +Version 4 +SHEET 1 880 680 +WIRE -288 -160 -336 -160 +WIRE 16 -160 -208 -160 +WIRE 16 -112 16 -160 +WIRE -32 -96 -96 -96 +WIRE 16 16 16 -16 +WIRE -336 112 -336 -160 +WIRE -336 112 -400 112 +WIRE -288 112 -336 112 +WIRE -96 112 -96 -96 +WIRE -96 112 -208 112 +WIRE 16 112 16 96 +WIRE 176 112 16 112 +WIRE 16 128 16 112 +WIRE -400 160 -400 112 +WIRE 16 240 16 208 +WIRE -96 320 -96 112 +WIRE -32 320 -96 320 +WIRE -336 384 -336 112 +WIRE -288 384 -336 384 +WIRE 16 384 16 336 +WIRE 16 384 -208 384 +FLAG -400 160 0 +SYMBOL nmos -32 240 R0 +SYMATTR InstName M1 +SYMATTR Value AO6408 +SYMBOL pmos -32 -16 M180 +SYMATTR InstName M2 +SYMATTR Value AO6407 +SYMBOL res 0 0 R0 +SYMATTR InstName R1 +SYMATTR Value 12k +SYMBOL res 0 112 R0 +SYMATTR InstName R2 +SYMATTR Value 12k +SYMBOL voltage -192 -160 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value 2 +SYMBOL voltage -192 112 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V2 +SYMATTR Value SINE(0 2 2) +SYMBOL voltage -192 384 R90 +WINDOW 0 -32 56 VBottom 0 +WINDOW 3 32 56 VTop 0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value -2 +TEXT -420 450 Left 0 !.tran 1 |