Constructed simulated ternary GULLIBLE gate

1 files changed, 51 insertions, 0 deletions

diff --git a/simulated/gullible.asc b/simulated/gullible.asc
new file mode 100644
index 0000000..8a5f06b
--- /dev/null
+++ b/simulated/gullible.asc
@@ -0,0 +1,51 @@
+Version 4
+SHEET 1 880 680
+WIRE 64 48 -96 48
+WIRE 192 64 128 64
+WIRE 224 96 128 96
+WIRE 368 96 288 96
+WIRE -48 112 -96 112
+WIRE 64 112 -16 112
+WIRE 224 112 160 112
+WIRE 80 128 80 112
+WIRE 240 128 240 112
+WIRE -48 176 -48 112
+WIRE 16 176 -48 176
+WIRE -16 240 -16 112
+WIRE -16 240 -96 240
+WIRE 16 240 16 176
+WIRE 64 240 16 240
+WIRE 192 240 192 64
+WIRE 224 240 192 240
+WIRE 160 256 160 112
+WIRE 160 256 128 256
+WIRE 224 288 128 288
+WIRE 368 288 288 288
+WIRE 64 304 -96 304
+WIRE 80 320 80 304
+WIRE 240 320 240 304
+FLAG -96 112 A+
+IOPIN -96 112 In
+FLAG -96 48 A-
+IOPIN -96 48 In
+FLAG -96 240 B-
+IOPIN -96 240 In
+FLAG -96 304 B+
+IOPIN -96 304 In
+FLAG 368 96 Y-
+IOPIN 368 96 Out
+FLAG 368 288 Y+
+IOPIN 368 288 Out
+FLAG 80 128 0
+FLAG 80 320 0
+FLAG 240 320 0
+FLAG 240 128 0
+SYMBOL Digital\\or 96 16 R0
+SYMATTR InstName A1
+SYMBOL Digital\\or 96 208 R0
+SYMATTR InstName A2
+SYMBOL Digital\\or 256 16 R0
+SYMATTR InstName A3
+SYMBOL Digital\\or 256 208 R0
+SYMATTR InstName A4
+TEXT 232 384 Left 0 ;Total = 20 transistors