Constructed simulated ternary decrement gate

1 files changed, 31 insertions, 0 deletions

diff --git a/simulated/decrement.asc b/simulated/decrement.asc
new file mode 100644
index 0000000..e111b21
--- /dev/null
+++ b/simulated/decrement.asc
@@ -0,0 +1,31 @@
+Version 4
+SHEET 1 880 680
+WIRE 112 48 -128 48
+WIRE 240 96 176 96
+WIRE 320 96 240 96
+WIRE 112 112 -48 112
+WIRE 128 128 128 112
+WIRE 240 176 240 96
+WIRE 240 176 64 176
+WIRE 64 224 64 176
+WIRE 112 224 64 224
+WIRE 320 272 176 272
+WIRE -48 288 -48 112
+WIRE -48 288 -128 288
+WIRE 112 288 -48 288
+WIRE 128 304 128 288
+FLAG 128 128 0
+FLAG 128 304 0
+FLAG -128 48 A-
+IOPIN -128 48 In
+FLAG -128 288 A+
+IOPIN -128 288 In
+FLAG 320 96 Y-
+IOPIN 320 96 Out
+FLAG 320 272 Y+
+IOPIN 320 272 Out
+SYMBOL Digital\\or 144 16 R0
+SYMATTR InstName A1
+SYMBOL Digital\\or 144 192 R0
+SYMATTR InstName A2
+TEXT 168 344 Left 0 ;Total = 8 transistors