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-rw-r--r--simulated/standard_inverter.asy64
1 files changed, 32 insertions, 32 deletions
diff --git a/simulated/standard_inverter.asy b/simulated/standard_inverter.asy
index 4a10402..d43138c 100644
--- a/simulated/standard_inverter.asy
+++ b/simulated/standard_inverter.asy
@@ -1,32 +1,32 @@
-Version 4
-SymbolType CELL
-LINE Normal 32 48 64 48
-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-LINE Normal 47 48 32 40
-LINE Normal -48 32 -48 48
-LINE Normal -64 32 -48 32
-LINE Normal -48 64 -48 48
-LINE Normal -64 64 -48 64
-LINE Normal 80 32 64 32
-LINE Normal 64 64 64 48
-LINE Normal 80 64 64 64
-LINE Normal 64 32 64 48
-TEXT 0 48 Center 0 NEG
-SYMATTR Description Inverter
-PIN -64 32 NONE 0
-PINATTR PinName A-
-PINATTR SpiceOrder 1
-PIN 80 32 NONE 0
-PINATTR PinName Y-
-PINATTR SpiceOrder 2
-PIN -64 64 NONE 8
-PINATTR PinName A+
-PINATTR SpiceOrder 3
-PIN 80 64 NONE 8
-PINATTR PinName Y+
-PINATTR SpiceOrder 4
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 NEG
+SYMATTR Description Inverter
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4