11 files changed, 0 insertions, 38 deletions
diff --git a/simulated/2_input_max.asc b/simulated/2_input_max.asc
index 8d5b5b2..52ff328 100644
--- a/simulated/2_input_max.asc
+++ b/simulated/2_input_max.asc
@@ -4,7 +4,6 @@ WIRE 144 16 -32 16
 WIRE 320 32 208 32
 WIRE 64 80 -32 80
 WIRE 144 80 96 80
-WIRE 160 96 160 80
 WIRE 96 144 96 80
 WIRE 96 144 32 144
 WIRE 32 208 32 144
@@ -13,7 +12,6 @@ WIRE 64 208 64 80
 WIRE 144 208 64 208
 WIRE 320 224 208 224
 WIRE 144 272 -32 272
-WIRE 160 288 160 272
 FLAG -32 16 A-
 IOPIN -32 16 In
 FLAG -32 80 A+
@@ -22,8 +20,6 @@ FLAG -32 208 B-
 IOPIN -32 208 In
 FLAG -32 272 B+
 IOPIN -32 272 In
-FLAG 160 96 0
-FLAG 160 288 0
 FLAG 320 32 Y-
 IOPIN 320 32 Out
 FLAG 320 224 Y+
diff --git a/simulated/2_input_min.asc b/simulated/2_input_min.asc
index 987253e..86179cb 100644
--- a/simulated/2_input_min.asc
+++ b/simulated/2_input_min.asc
@@ -4,7 +4,6 @@ WIRE 144 16 -32 16
 WIRE 320 32 208 32
 WIRE 64 80 -32 80
 WIRE 144 80 96 80
-WIRE 160 96 160 80
 WIRE 96 144 96 80
 WIRE 96 144 32 144
 WIRE 32 208 32 144
@@ -13,7 +12,6 @@ WIRE 64 208 64 80
 WIRE 144 208 64 208
 WIRE 320 224 208 224
 WIRE 144 272 -32 272
-WIRE 160 288 160 272
 FLAG -32 16 A-
 IOPIN -32 16 In
 FLAG -32 80 A+
@@ -22,8 +20,6 @@ FLAG -32 208 B-
 IOPIN -32 208 In
 FLAG -32 272 B+
 IOPIN -32 272 In
-FLAG 160 96 0
-FLAG 160 288 0
 FLAG 320 32 Y-
 IOPIN 320 32 Out
 FLAG 320 224 Y+
diff --git a/simulated/consensus.asc b/simulated/consensus.asc
index cdee660..6569a51 100644
--- a/simulated/consensus.asc
+++ b/simulated/consensus.asc
@@ -4,7 +4,6 @@ WIRE 144 16 -32 16
 WIRE 320 32 208 32
 WIRE 64 80 -32 80
 WIRE 144 80 96 80
-WIRE 160 96 160 80
 WIRE 96 144 96 80
 WIRE 96 144 32 144
 WIRE 32 208 32 144
@@ -13,7 +12,6 @@ WIRE 64 208 64 80
 WIRE 144 208 64 208
 WIRE 320 224 208 224
 WIRE 144 272 -32 272
-WIRE 160 288 160 272
 FLAG -32 16 A-
 IOPIN -32 16 In
 FLAG -32 80 A+
@@ -22,8 +20,6 @@ FLAG -32 208 B-
 IOPIN -32 208 In
 FLAG -32 272 B+
 IOPIN -32 272 In
-FLAG 160 96 0
-FLAG 160 288 0
 FLAG 320 32 Y-
 IOPIN 320 32 Out
 FLAG 320 224 Y+
diff --git a/simulated/decrement.asc b/simulated/decrement.asc
index e111b21..cb2d762 100644
--- a/simulated/decrement.asc
+++ b/simulated/decrement.asc
@@ -4,7 +4,6 @@ WIRE 112 48 -128 48
 WIRE 240 96 176 96
 WIRE 320 96 240 96
 WIRE 112 112 -48 112
-WIRE 128 128 128 112
 WIRE 240 176 240 96
 WIRE 240 176 64 176
 WIRE 64 224 64 176
@@ -13,9 +12,6 @@ WIRE 320 272 176 272
 WIRE -48 288 -48 112
 WIRE -48 288 -128 288
 WIRE 112 288 -48 288
-WIRE 128 304 128 288
-FLAG 128 128 0
-FLAG 128 304 0
 FLAG -128 48 A-
 IOPIN -128 48 In
 FLAG -128 288 A+
diff --git a/simulated/gullible.asc b/simulated/gullible.asc
index 8a5f06b..0589e69 100644
--- a/simulated/gullible.asc
+++ b/simulated/gullible.asc
@@ -7,8 +7,6 @@ WIRE 368 96 288 96
 WIRE -48 112 -96 112
 WIRE 64 112 -16 112
 WIRE 224 112 160 112
-WIRE 80 128 80 112
-WIRE 240 128 240 112
 WIRE -48 176 -48 112
 WIRE 16 176 -48 176
 WIRE -16 240 -16 112
@@ -22,8 +20,6 @@ WIRE 160 256 128 256
 WIRE 224 288 128 288
 WIRE 368 288 288 288
 WIRE 64 304 -96 304
-WIRE 80 320 80 304
-WIRE 240 320 240 304
 FLAG -96 112 A+
 IOPIN -96 112 In
 FLAG -96 48 A-
@@ -36,10 +32,6 @@ FLAG 368 96 Y-
 IOPIN 368 96 Out
 FLAG 368 288 Y+
 IOPIN 368 288 Out
-FLAG 80 128 0
-FLAG 80 320 0
-FLAG 240 320 0
-FLAG 240 128 0
 SYMBOL Digital\\or 96 16 R0
 SYMATTR InstName A1
 SYMBOL Digital\\or 96 208 R0
diff --git a/simulated/increment.asc b/simulated/increment.asc
index 4bc1e9d..f2f5fcb 100644
--- a/simulated/increment.asc
+++ b/simulated/increment.asc
@@ -4,7 +4,6 @@ WIRE -48 48 -128 48
 WIRE 112 48 -48 48
 WIRE 320 96 176 96
 WIRE 112 112 64 112
-WIRE 128 128 128 112
 WIRE 64 176 64 112
 WIRE 240 176 64 176
 WIRE -48 224 -48 48
@@ -13,9 +12,6 @@ WIRE 240 272 240 176
 WIRE 240 272 176 272
 WIRE 320 272 240 272
 WIRE 112 288 -128 288
-WIRE 128 304 128 288
-FLAG 128 128 0
-FLAG 128 304 0
 FLAG -128 48 A-
 IOPIN -128 48 In
 FLAG -128 288 A+
diff --git a/simulated/is_false.asc b/simulated/is_false.asc
index 3202fdc..8d7d1d6 100644
--- a/simulated/is_false.asc
+++ b/simulated/is_false.asc
@@ -3,11 +3,9 @@ SHEET 1 880 680
 WIRE 32 64 -48 64
 WIRE 96 64 32 64
 WIRE 240 64 160 64
-WIRE 96 96 96 80
 WIRE 0 128 -48 128
 WIRE 32 128 32 64
 WIRE 240 128 32 128
-FLAG 96 96 0
 FLAG 240 64 Y-
 IOPIN 240 64 Out
 FLAG 240 128 Y+
diff --git a/simulated/is_true.asc b/simulated/is_true.asc
index 1c96f52..0839114 100644
--- a/simulated/is_true.asc
+++ b/simulated/is_true.asc
@@ -3,11 +3,9 @@ SHEET 1 880 680
 WIRE 0 64 -48 64
 WIRE 96 64 32 64
 WIRE 240 64 160 64
-WIRE 96 96 96 80
 WIRE 32 128 32 64
 WIRE 32 128 -48 128
 WIRE 240 128 32 128
-FLAG 96 96 0
 FLAG 240 64 Y-
 IOPIN 240 64 Out
 FLAG 240 128 Y+
diff --git a/simulated/is_unknown.asc b/simulated/is_unknown.asc
index 2ea7462..bc40aa2 100644
--- a/simulated/is_unknown.asc
+++ b/simulated/is_unknown.asc
@@ -4,8 +4,6 @@ WIRE 64 64 -48 64
 WIRE 240 80 128 80
 WIRE 240 112 128 112
 WIRE 64 128 -48 128
-WIRE 80 144 80 128
-FLAG 80 144 0
 FLAG 240 80 Y-
 IOPIN 240 80 Out
 FLAG 240 112 Y+
diff --git a/simulated/negative_threshold_inverter.asc b/simulated/negative_threshold_inverter.asc
index 3202fdc..8d7d1d6 100644
--- a/simulated/negative_threshold_inverter.asc
+++ b/simulated/negative_threshold_inverter.asc
@@ -3,11 +3,9 @@ SHEET 1 880 680
 WIRE 32 64 -48 64
 WIRE 96 64 32 64
 WIRE 240 64 160 64
-WIRE 96 96 96 80
 WIRE 0 128 -48 128
 WIRE 32 128 32 64
 WIRE 240 128 32 128
-FLAG 96 96 0
 FLAG 240 64 Y-
 IOPIN 240 64 Out
 FLAG 240 128 Y+
diff --git a/simulated/positive_threshold_inverter.asc b/simulated/positive_threshold_inverter.asc
index c8066ec..983226c 100644
--- a/simulated/positive_threshold_inverter.asc
+++ b/simulated/positive_threshold_inverter.asc
@@ -6,8 +6,6 @@ WIRE 32 128 32 64
 WIRE 32 128 -48 128
 WIRE 96 128 32 128
 WIRE 240 128 160 128
-WIRE 96 160 96 144
-FLAG 96 160 0
 FLAG 240 64 Y-
 IOPIN 240 64 Out
 FLAG 240 128 Y+