blob: b238c105db43fa56d8434d3378b7dee914b3168d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
Implementations of ternary logic gates as described by Douglas W Jones. All implementations were constructed in LTSpice, and all have matching symbols supplied for use as subcircuits.
For information on the behaviour of the gates, see http://homepage.cs.uiowa.edu/~jones/ternary/logic.shtml
/CMOS
Uses CMOS transistor logic. Custom MOSFETs are employed in order to ensure correct threshold voltages as well as allow the use of P-channel depletion mode MOSFETs. 8 different MOSFETs are used - 2 levels each for P-channel, N-channel, and for enhancement and depletion modes.
/RMOS
Uses CMOS transistor logic with resistors to pull the output to the middle logical value where necessary. Custom MOSFETs are employed to ensure correct threshold voltages. Unlike CMOS, circuits are constructed as to only require 2 different MOSFETs - one P-channel and one N-channel with the same threshold voltage, both enhancement mode.
/simulated
Ternary values are encoded in a pair of binary values, one to signal whether the ternary value is positive, and one for negative. This gives the mapping:
+ -> 01
0 -> 00
- -> 10
Gates are then constructed using LTSpice's built in binary logic gate functions. The value of 11 is illegal.
|
