simulated - ternary-logic - Ternary logic gate schematics

index : ternary-logic

Ternary logic gate schematics

Jed Barber

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Mode	Name	Size
-rw-r--r--	standard_inverter.asc	355	log plain

generated by cgit (git 2.30.0) at 2024-12-25 18:24:51 +0000