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authorJed Barber <jjbarber@y7mail.com>2014-03-02 17:45:07 +1100
committerJed Barber <jjbarber@y7mail.com>2014-03-02 17:45:07 +1100
commit13151dd028cafb4d4b5de42d8754970ac9dffc04 (patch)
tree30705b5cca33fda885a21addc8544c38b5c9d173
parent9a13d5cc14326573c1908f7b9bbb1d06a9f900b5 (diff)
Updated readme
-rw-r--r--readme.txt8
1 files changed, 2 insertions, 6 deletions
diff --git a/readme.txt b/readme.txt
index 475b556..b238c10 100644
--- a/readme.txt
+++ b/readme.txt
@@ -9,18 +9,14 @@ For information on the behaviour of the gates, see http://homepage.cs.uiowa.edu/
/CMOS
-Uses CMOS transistor logic. Custom MOSFETs are employed in order to ensure correct threshold voltages as well as allow the use of P-channel depletion mode MOSFETs.
+Uses CMOS transistor logic. Custom MOSFETs are employed in order to ensure correct threshold voltages as well as allow the use of P-channel depletion mode MOSFETs. 8 different MOSFETs are used - 2 levels each for P-channel, N-channel, and for enhancement and depletion modes.
/RMOS
-Uses CMOS transistor logic with resistors to pull the output to the middle logical value where necessary. Custom MOSFETs are employed to ensure correct threshold voltages.
-
-There are at least two ways of constructing this. The first way involves setting the thresholds of the positive and negative MOSFET networks to overlap, and placing resistors between each of them and the output. The output is then pulled to the middle value when both networks are active. The second way involves merely replacing one of the MOSFET networks from a CMOS circuit with a resistor.
-
-Interestingly, the first approach does not work properly for dyadic gates.
+Uses CMOS transistor logic with resistors to pull the output to the middle logical value where necessary. Custom MOSFETs are employed to ensure correct threshold voltages. Unlike CMOS, circuits are constructed as to only require 2 different MOSFETs - one P-channel and one N-channel with the same threshold voltage, both enhancement mode.