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+Implementations of ternary logic gates as described by Douglas W Jones. All implementations were constructed in LTSpice, and all have matching symbols supplied for use as subcircuits.
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+For information on the behaviour of the gates, see http://homepage.cs.uiowa.edu/~jones/ternary/logic.shtml
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+/CMOS
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+Uses CMOS transistor logic. Custom MOSFETs are employed in order to ensure correct threshold voltages as well as allow the use of P-channel depletion mode MOSFETs.
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+/RMOS
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+Uses CMOS transistor logic with resistors to pull the output to the middle logical value where necessary.
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+/simulated
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+Ternary values are encoded in a pair of binary values, one to signal whether the ternary value is positive, and one for negative. This gives the mapping:
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++ -> 01
+0 -> 00
+- -> 10
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+Gates are then constructed using LTSpice's built in binary logic gate functions. The value of 11 is illegal.
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