Added symbols for the rest of the gates

10 files changed, 385 insertions, 0 deletions

diff --git a/simulated/2_input_max.asy b/simulated/2_input_max.asy
new file mode 100644
index 0000000..f900f55
--- /dev/null
+++ b/simulated/2_input_max.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 MAX
+SYMATTR Description 2-input MAX gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6
diff --git a/simulated/2_input_min.asy b/simulated/2_input_min.asy
new file mode 100644
index 0000000..ed919e3
--- /dev/null
+++ b/simulated/2_input_min.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 MIN
+SYMATTR Description 2-input MIN gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6
diff --git a/simulated/buffer.asy b/simulated/buffer.asy
new file mode 100644
index 0000000..4e87477
--- /dev/null
+++ b/simulated/buffer.asy
@@ -0,0 +1,32 @@
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -48 64 -48 48
+LINE Normal -64 64 -48 64
+LINE Normal 80 32 64 32
+LINE Normal 64 64 64 48
+LINE Normal 80 64 64 64
+LINE Normal 64 32 64 48
+TEXT 0 48 Center 0 BUF
+SYMATTR Description Buffer
+PIN -64 32 NONE 0
+PINATTR PinName A-
+PINATTR SpiceOrder 1
+PIN 80 32 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 2
+PIN -64 64 NONE 8
+PINATTR PinName A+
+PINATTR SpiceOrder 3
+PIN 80 64 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 4
diff --git a/simulated/clamp_down.asy b/simulated/clamp_down.asy
new file mode 100644
index 0000000..44deb75
--- /dev/null
+++ b/simulated/clamp_down.asy
@@ -0,0 +1,33 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -64 48 -48 48
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 64 80 64 64
+LINE Normal 80 80 64 80
+TEXT 1 48 Center 0 MIN
+TEXT -63 80 Left 0 0
+SYMATTR Description CLAMP DOWN gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN 80 80 NONE 0
+PINATTR PinName Y+
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 8
+PINATTR PinName Y-
+PINATTR SpiceOrder 4
diff --git a/simulated/clamp_up.asy b/simulated/clamp_up.asy
new file mode 100644
index 0000000..26415b5
--- /dev/null
+++ b/simulated/clamp_up.asy
@@ -0,0 +1,33 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -64 48 -48 48
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 64 80 64 64
+LINE Normal 80 80 64 80
+TEXT 1 48 Center 0 MAX
+TEXT -63 80 Left 0 0
+SYMATTR Description CLAMP UP gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN 80 80 NONE 0
+PINATTR PinName Y+
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 8
+PINATTR PinName Y-
+PINATTR SpiceOrder 4
diff --git a/simulated/consensus.asy b/simulated/consensus.asy
new file mode 100644
index 0000000..03c6620
--- /dev/null
+++ b/simulated/consensus.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 CON
+SYMATTR Description 2-input consensus gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6
diff --git a/simulated/equality.asy b/simulated/equality.asy
new file mode 100644
index 0000000..1c81763
--- /dev/null
+++ b/simulated/equality.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 =
+SYMATTR Description 2-input equality gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6
diff --git a/simulated/gullible.asy b/simulated/gullible.asy
new file mode 100644
index 0000000..d7cf229
--- /dev/null
+++ b/simulated/gullible.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 GUL
+SYMATTR Description 2-input gullible gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6
diff --git a/simulated/sum.asy b/simulated/sum.asy
new file mode 100644
index 0000000..f72c0e1
--- /dev/null
+++ b/simulated/sum.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 SUM
+SYMATTR Description SUM gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6
diff --git a/simulated/xor.asy b/simulated/xor.asy
new file mode 100644
index 0000000..a2aa152
--- /dev/null
+++ b/simulated/xor.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+LINE Normal -48 32 -48 48
+LINE Normal -64 32 -48 32
+LINE Normal -64 48 -48 48
+LINE Normal -48 96 -48 80
+LINE Normal -64 96 -48 96
+LINE Normal -64 80 -48 80
+LINE Normal 64 48 64 64
+LINE Normal 80 48 64 48
+LINE Normal 80 80 64 80
+LINE Normal 64 80 64 64
+TEXT 1 48 Center 0 XOR
+SYMATTR Description XOR gate
+PIN -64 48 NONE 0
+PINATTR PinName A+
+PINATTR SpiceOrder 1
+PIN -64 80 NONE 0
+PINATTR PinName B-
+PINATTR SpiceOrder 2
+PIN 80 48 NONE 0
+PINATTR PinName Y-
+PINATTR SpiceOrder 3
+PIN -64 32 NONE 8
+PINATTR PinName A-
+PINATTR SpiceOrder 4
+PIN -64 96 NONE 8
+PINATTR PinName B+
+PINATTR SpiceOrder 5
+PIN 80 80 NONE 8
+PINATTR PinName Y+
+PINATTR SpiceOrder 6