Cleaned up symbol attribute details

17 files changed, 18 insertions, 69 deletions

diff --git a/CMOS/2_input_antimax.asy b/CMOS/2_input_antimax.asy
index c5c0156..768c42a 100644
--- a/CMOS/2_input_antimax.asy
+++ b/CMOS/2_input_antimax.asy
@@ -12,11 +12,8 @@ LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 0 77 Center 0 MAX
 TEXT 0 52 Center 0 ANTI
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description 2-input ANTIMAX gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_antimin.asy b/CMOS/2_input_antimin.asy
index 27224f7..db357ec 100644
--- a/CMOS/2_input_antimin.asy
+++ b/CMOS/2_input_antimin.asy
@@ -12,11 +12,8 @@ LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 0 77 Center 0 MIN
 TEXT 0 52 Center 0 ANTI
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description 2-input ANTIMIN gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_consensus.asy b/CMOS/2_input_consensus.asy
index 2d4aef1..4604eb5 100644
--- a/CMOS/2_input_consensus.asy
+++ b/CMOS/2_input_consensus.asy
@@ -10,11 +10,8 @@ LINE Normal 32 96 32 32
 LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 0 52 Center 0 CON
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description 2-input consensus gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_inverting_consensus.asy b/CMOS/2_input_inverting_consensus.asy
index c6ff74e..f6cc640 100644
--- a/CMOS/2_input_inverting_consensus.asy
+++ b/CMOS/2_input_inverting_consensus.asy
@@ -11,11 +11,8 @@ LINE Normal 32 96 32 32
 LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 0 52 Center 0 CON
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description 2-input inverting consensus
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_max.asy b/CMOS/2_input_max.asy
index b65f878..4470927 100644
--- a/CMOS/2_input_max.asy
+++ b/CMOS/2_input_max.asy
@@ -10,11 +10,8 @@ LINE Normal 32 96 32 32
 LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 1 48 Center 0 MAX
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description 2-input MAX gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/2_input_min.asy b/CMOS/2_input_min.asy
index d04c400..df47c15 100644
--- a/CMOS/2_input_min.asy
+++ b/CMOS/2_input_min.asy
@@ -10,11 +10,8 @@ LINE Normal 32 96 32 32
 LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 1 48 Center 0 MIN
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description 2-input MIN gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/buffer.asy b/CMOS/buffer.asy
index b26597f..35ccb12 100644
--- a/CMOS/buffer.asy
+++ b/CMOS/buffer.asy
@@ -8,11 +8,8 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 TEXT 0 48 Center 0 BUF
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description Buffer
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/clamp_down.asy b/CMOS/clamp_down.asy
index 9d761fb..8888ac4 100644
--- a/CMOS/clamp_down.asy
+++ b/CMOS/clamp_down.asy
@@ -11,11 +11,8 @@ LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 1 48 Center 0 MIN
 TEXT -63 80 Left 0 0
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description CLAMP DOWN gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/clamp_up.asy b/CMOS/clamp_up.asy
index 3fc2407..adcf7d9 100644
--- a/CMOS/clamp_up.asy
+++ b/CMOS/clamp_up.asy
@@ -11,11 +11,8 @@ LINE Normal -32 96 32 96
 LINE Normal -32 32 -32 96
 TEXT 1 48 Center 0 MAX
 TEXT -63 80 Left 0 0
-WINDOW 0 -16 16 Left 0
-SYMATTR Description 2-input NAND gate
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description CLAMP UP gate
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/decrement.asy b/CMOS/decrement.asy
index 7019095..c178fc5 100644
--- a/CMOS/decrement.asy
+++ b/CMOS/decrement.asy
@@ -8,11 +8,8 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 TEXT 0 48 Center 0 -1
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description Decrement gate
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/increment.asy b/CMOS/increment.asy
index e4b2602..c7a2b36 100644
--- a/CMOS/increment.asy
+++ b/CMOS/increment.asy
@@ -8,11 +8,8 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 TEXT 0 48 Center 0 +1
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description Increment gate
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/is_false.asy b/CMOS/is_false.asy
index 5040804..6c8c5a2 100644
--- a/CMOS/is_false.asy
+++ b/CMOS/is_false.asy
@@ -8,11 +8,8 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 TEXT 0 48 Center 0 =-
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description IS FALSE gate
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/is_true.asy b/CMOS/is_true.asy
index 4beb63f..42c7c1b 100644
--- a/CMOS/is_true.asy
+++ b/CMOS/is_true.asy
@@ -8,11 +8,8 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 TEXT 0 48 Center 0 =+
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description IS TRUE gate
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/is_unknown.asy b/CMOS/is_unknown.asy
index c63122a..94fa3b7 100644
--- a/CMOS/is_unknown.asy
+++ b/CMOS/is_unknown.asy
@@ -8,11 +8,8 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 TEXT 0 48 Center 0 =0
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description IS UNKNOWN gate
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/negative_threshold_inverter.asy b/CMOS/negative_threshold_inverter.asy
index 2a16bc2..d285f5c 100644
--- a/CMOS/negative_threshold_inverter.asy
+++ b/CMOS/negative_threshold_inverter.asy
@@ -9,11 +9,8 @@ LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 LINE Normal 47 48 32 40
 TEXT 0 48 Center 0 NTI
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description Negative threshold inverter
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/positive_threshold_inverter.asy b/CMOS/positive_threshold_inverter.asy
index b149977..cea7fec 100644
--- a/CMOS/positive_threshold_inverter.asy
+++ b/CMOS/positive_threshold_inverter.asy
@@ -9,11 +9,8 @@ LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 LINE Normal 47 48 32 40
 TEXT 0 48 Center 0 PTI
-WINDOW 0 -15 16 Left 0
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description Positive threshold inverter
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1
diff --git a/CMOS/standard_inverter.asy b/CMOS/standard_inverter.asy
index 93e3b3c..db5b740 100644
--- a/CMOS/standard_inverter.asy
+++ b/CMOS/standard_inverter.asy
@@ -8,12 +8,9 @@ LINE Normal -32 64 32 64
 LINE Normal -32 32 -32 64
 LINE Normal 32 40 32 48
 LINE Normal 47 48 32 40
-TEXT 0 48 Center 0 STI
-WINDOW 0 -15 16 Left 0
+TEXT 0 48 Center 0 NEG
 SYMATTR Prefix X
-SYMATTR SpiceModel VDD 0
-SYMATTR Description Inverting buffer
-SYMATTR SpiceLine VDD=5  SPEED=1.0  TRIPDT=5e-9
+SYMATTR Description Inverter
 PIN -48 48 NONE 0
 PINATTR PinName A
 PINATTR SpiceOrder 1