| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-02-13 | Constructed simulated ternary 2 input MIN gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary 2 input MAX gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary CLAMP DOWN gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary CLAMP UP gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary buffer | Jed Barber |
| 2014-02-13 | Made symbols for all simulated ternary gates so far | Jed Barber |
| 2014-02-13 | Constructed simulated ternary IS FALSE gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary IS UNKNOWN gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary IS TRUE gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary increment gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary decrement gate | Jed Barber |
| 2014-02-13 | Constructed simulated ternary negative threshold inverter | Jed Barber |
| 2014-02-13 | Constructed simulated ternary positive threshold inverter | Jed Barber |
| 2014-02-13 | Constructed simulated ternary standard inverter | Jed Barber |
 |
index : ternary-logic | |
| Ternary logic gate schematics | Jed Barber |
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