Old uncommitted changesHEAD master

author: Jed Barber <jjbarber@y7mail.com> 2016-12-15 14:26:29 +1100
committer: Jed Barber <jjbarber@y7mail.com> 2016-12-15 14:26:29 +1100
commit: 76682bade38a8b2d58490ddbb80cb627a2b2ad1b (patch)
tree: 2b6aa35854a5a9488e419ddf9792d4037bf697d5 /CMOS
parent: 1e7286b071bcb070ddaa95f09d29614bad7a282d (diff)
49 files changed, 2493 insertions, 2493 deletions
diff --git a/CMOS/2_input_antimax.asc b/CMOS/2_input_antimax.asc
index d74f80e..4675cc2 100644
--- a/CMOS/2_input_antimax.asc
+++ b/CMOS/2_input_antimax.asc
@@ -1,105 +1,105 @@
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-SYMATTR Value P-ENH
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-SYMBOL nmos -16 400 R0
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-SYMATTR Value N-ENH
-SYMBOL nmos 336 -16 R0
-SYMATTR InstName M5
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-SYMATTR InstName M6
-SYMATTR Value N-DLOW
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-SYMATTR Value P-DLOW
-SYMBOL pmos 448 336 R0
-SYMATTR InstName M8
-SYMATTR Value P-DLOW
-SYMBOL voltage -400 -192 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V3
-SYMATTR Value 1
-SYMBOL voltage -400 544 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V4
-SYMATTR Value -1
-TEXT 328 -176 Left 0 !.inc ./custom.mos
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+SYMATTR InstName M1
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+SYMBOL pmos -144 80 M180
+SYMATTR InstName M2
+SYMATTR Value P-ENH
+SYMBOL nmos -256 400 R0
+SYMATTR InstName M3
+SYMATTR Value N-ENH
+SYMBOL nmos -16 400 R0
+SYMATTR InstName M4
+SYMATTR Value N-ENH
+SYMBOL nmos 336 -16 R0
+SYMATTR InstName M5
+SYMATTR Value N-DLOW
+SYMBOL nmos 576 -16 R0
+SYMATTR InstName M6
+SYMATTR Value N-DLOW
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+SYMATTR InstName M7
+SYMATTR Value P-DLOW
+SYMBOL pmos 448 336 R0
+SYMATTR InstName M8
+SYMATTR Value P-DLOW
+SYMBOL voltage -400 -192 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value 1
+SYMBOL voltage -400 544 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V4
+SYMATTR Value -1
+TEXT 328 -176 Left 0 !.inc ./custom.mos
diff --git a/CMOS/2_input_antimax.asy b/CMOS/2_input_antimax.asy
index e29234c..8ef0d80 100644
--- a/CMOS/2_input_antimax.asy
+++ b/CMOS/2_input_antimax.asy
@@ -1,24 +1,24 @@
-Version 4
-SymbolType CELL
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-LINE Normal 32 56 48 64
-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 0 77 Center 0 MAX
-TEXT 0 52 Center 0 ANTI
-SYMATTR Description 2-input ANTIMAX gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 56 48 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 0 77 Center 0 MAX
+TEXT 0 52 Center 0 ANTI
+SYMATTR Description 2-input ANTIMAX gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/2_input_antimin.asc b/CMOS/2_input_antimin.asc
index 14b61d2..79255dc 100644
--- a/CMOS/2_input_antimin.asc
+++ b/CMOS/2_input_antimin.asc
@@ -1,103 +1,103 @@
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-SYMATTR Value P-ENH
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-SYMATTR InstName M2
-SYMATTR Value P-ENH
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-SYMATTR InstName M3
-SYMATTR Value N-ENH
-SYMBOL nmos -144 352 R0
-SYMATTR InstName M4
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-SYMBOL voltage -432 -208 R90
-WINDOW 0 -32 56 VBottom 0
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-WINDOW 0 -32 56 VBottom 0
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-SYMATTR Value -1
-SYMBOL nmos 320 368 R0
-SYMATTR InstName M5
-SYMATTR Value N-DLOW
-SYMBOL nmos 320 240 R0
-SYMATTR InstName M6
-SYMATTR Value N-DLOW
-SYMBOL pmos 208 -16 R0
-SYMATTR InstName M7
-SYMATTR Value P-DLOW
-SYMBOL pmos 464 -16 R0
-SYMATTR InstName M8
-SYMATTR Value P-DLOW
-TEXT 360 -184 Left 0 !.inc ./custom.mos
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+SYMBOL pmos 464 -16 R0
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+SYMATTR Value P-DLOW
+TEXT 360 -184 Left 0 !.inc ./custom.mos
diff --git a/CMOS/2_input_antimin.asy b/CMOS/2_input_antimin.asy
index 1b33509..2e9850b 100644
--- a/CMOS/2_input_antimin.asy
+++ b/CMOS/2_input_antimin.asy
@@ -1,24 +1,24 @@
-Version 4
-SymbolType CELL
-LINE Normal 48 64 32 64
-LINE Normal 32 56 48 64
-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 0 77 Center 0 MIN
-TEXT 0 52 Center 0 ANTI
-SYMATTR Description 2-input ANTIMIN gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
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+LINE Normal 32 64 32 56
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+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 0 77 Center 0 MIN
+TEXT 0 52 Center 0 ANTI
+SYMATTR Description 2-input ANTIMIN gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/2_input_max.asc b/CMOS/2_input_max.asc
index 6edc382..7787925 100644
--- a/CMOS/2_input_max.asc
+++ b/CMOS/2_input_max.asc
@@ -1,15 +1,15 @@
-Version 4
-SHEET 1 880 680
-WIRE 80 160 64 160
-WIRE 320 176 304 176
-WIRE 80 192 64 192
-FLAG 64 160 A
-IOPIN 64 160 In
-FLAG 64 192 B
-IOPIN 64 192 In
-FLAG 320 176 Y
-IOPIN 320 176 Out
-SYMBOL .\\2_input_antimax 128 112 R0
-SYMATTR InstName U1
-SYMBOL .\\standard_inverter 240 128 R0
-SYMATTR InstName U2
+Version 4
+SHEET 1 880 680
+WIRE 80 160 64 160
+WIRE 320 176 304 176
+WIRE 80 192 64 192
+FLAG 64 160 A
+IOPIN 64 160 In
+FLAG 64 192 B
+IOPIN 64 192 In
+FLAG 320 176 Y
+IOPIN 320 176 Out
+SYMBOL .\\2_input_antimax 128 112 R0
+SYMATTR InstName U1
+SYMBOL .\\standard_inverter 240 128 R0
+SYMATTR InstName U2
diff --git a/CMOS/2_input_max.asy b/CMOS/2_input_max.asy
index 5552b62..a398f78 100644
--- a/CMOS/2_input_max.asy
+++ b/CMOS/2_input_max.asy
@@ -1,22 +1,22 @@
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-SymbolType CELL
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-LINE Normal 64 64 48 64
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-LINE Normal 32 32 -32 32
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-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 1 48 Center 0 MAX
-SYMATTR Description 2-input MAX gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
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+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 1 48 Center 0 MAX
+SYMATTR Description 2-input MAX gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/2_input_min.asc b/CMOS/2_input_min.asc
index 6f991fc..becb35c 100644
--- a/CMOS/2_input_min.asc
+++ b/CMOS/2_input_min.asc
@@ -1,15 +1,15 @@
-Version 4
-SHEET 1 880 680
-WIRE 80 160 64 160
-WIRE 320 176 304 176
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-IOPIN 64 160 In
-FLAG 64 192 B
-IOPIN 64 192 In
-FLAG 320 176 Y
-IOPIN 320 176 Out
-SYMBOL .\\2_input_antimin 128 112 R0
-SYMATTR InstName U1
-SYMBOL .\\standard_inverter 240 128 R0
-SYMATTR InstName U2
+Version 4
+SHEET 1 880 680
+WIRE 80 160 64 160
+WIRE 320 176 304 176
+WIRE 80 192 64 192
+FLAG 64 160 A
+IOPIN 64 160 In
+FLAG 64 192 B
+IOPIN 64 192 In
+FLAG 320 176 Y
+IOPIN 320 176 Out
+SYMBOL .\\2_input_antimin 128 112 R0
+SYMATTR InstName U1
+SYMBOL .\\standard_inverter 240 128 R0
+SYMATTR InstName U2
diff --git a/CMOS/2_input_min.asy b/CMOS/2_input_min.asy
index 0efa86d..3e5b13c 100644
--- a/CMOS/2_input_min.asy
+++ b/CMOS/2_input_min.asy
@@ -1,22 +1,22 @@
-Version 4
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-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 1 48 Center 0 MIN
-SYMATTR Description 2-input MIN gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
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+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 1 48 Center 0 MIN
+SYMATTR Description 2-input MIN gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/3_input_antimax.asc b/CMOS/3_input_antimax.asc
index 4a394af..b32cc6d 100644
--- a/CMOS/3_input_antimax.asc
+++ b/CMOS/3_input_antimax.asc
@@ -1,135 +1,135 @@
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+SYMATTR Value P-DLOW
+SYMBOL pmos 608 368 R0
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+SYMATTR Value P-DLOW
+SYMBOL voltage -144 -256 R90
+WINDOW 0 -32 56 VBottom 0
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+WINDOW 123 0 0 Left 0
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+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -144 576 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
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+SYMATTR InstName V2
+SYMATTR Value -1
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diff --git a/CMOS/3_input_antimin.asc b/CMOS/3_input_antimin.asc
index 67da610..e920541 100644
--- a/CMOS/3_input_antimin.asc
+++ b/CMOS/3_input_antimin.asc
@@ -1,137 +1,137 @@
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-SYMBOL pmos 384 368 R0
-SYMATTR InstName M11
-SYMATTR Value P-DLOW
-SYMBOL pmos 768 368 R0
-SYMATTR InstName M12
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-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V1
-SYMATTR Value 1
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-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
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-SYMATTR Value -1
-TEXT 224 -248 Left 0 !.inc ./custom.mos
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+SYMATTR InstName M11
+SYMATTR Value P-DLOW
+SYMBOL pmos 768 368 R0
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+SYMATTR Value P-DLOW
+SYMBOL voltage -112 -288 R90
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+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -112 544 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
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+SYMATTR InstName V2
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+TEXT 224 -248 Left 0 !.inc ./custom.mos
diff --git a/CMOS/buffer.asc b/CMOS/buffer.asc
index 5947710..3d8de74 100644
--- a/CMOS/buffer.asc
+++ b/CMOS/buffer.asc
@@ -1,12 +1,12 @@
-Version 4
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-WIRE 0 80 -16 80
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-SYMBOL .\\standard_inverter 48 32 R0
-SYMATTR InstName U1
-SYMBOL .\\standard_inverter 160 32 R0
-SYMATTR InstName U2
+Version 4
+SHEET 1 944 680
+WIRE 0 80 -16 80
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+FLAG 240 80 Y
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+SYMBOL .\\standard_inverter 48 32 R0
+SYMATTR InstName U1
+SYMBOL .\\standard_inverter 160 32 R0
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diff --git a/CMOS/buffer.asy b/CMOS/buffer.asy
index e92d13d..a659405 100644
--- a/CMOS/buffer.asy
+++ b/CMOS/buffer.asy
@@ -1,17 +1,17 @@
-Version 4
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-LINE Normal 32 48 64 48
-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-TEXT 0 48 Center 0 BUF
-SYMATTR Description Buffer
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
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+LINE Normal -32 64 32 64
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+LINE Normal 32 40 32 48
+TEXT 0 48 Center 0 BUF
+SYMATTR Description Buffer
+PIN -48 48 NONE 0
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+PIN 64 48 NONE 0
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diff --git a/CMOS/clamp_down.asc b/CMOS/clamp_down.asc
index a465876..2ca37a8 100644
--- a/CMOS/clamp_down.asc
+++ b/CMOS/clamp_down.asc
@@ -1,40 +1,40 @@
-Version 4
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-WINDOW 39 0 0 Left 0
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-SYMATTR InstName M4
-SYMATTR Value N-ENH
-SYMBOL .\\negative_threshold_inverter -48 96 R0
-SYMATTR InstName U1
-TEXT 424 -136 Left 0 !.inc ./custom.mos
+Version 4
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+SYMATTR InstName M4
+SYMATTR Value N-ENH
+SYMBOL .\\negative_threshold_inverter -48 96 R0
+SYMATTR InstName U1
+TEXT 424 -136 Left 0 !.inc ./custom.mos
diff --git a/CMOS/clamp_down.asy b/CMOS/clamp_down.asy
index 3fccbd7..cc88457 100644
--- a/CMOS/clamp_down.asy
+++ b/CMOS/clamp_down.asy
@@ -1,20 +1,20 @@
-Version 4
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-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 1 48 Center 0 MIN
-TEXT -63 80 Left 0 0
-SYMATTR Description CLAMP DOWN gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
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+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 1 48 Center 0 MIN
+TEXT -63 80 Left 0 0
+SYMATTR Description CLAMP DOWN gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/clamp_up.asc b/CMOS/clamp_up.asc
index 1205e4a..ae5ada0 100644
--- a/CMOS/clamp_up.asc
+++ b/CMOS/clamp_up.asc
@@ -1,38 +1,38 @@
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+TEXT -136 296 Left 0 !.inc ./custom.mos
diff --git a/CMOS/clamp_up.asy b/CMOS/clamp_up.asy
index b4ebc93..5504d00 100644
--- a/CMOS/clamp_up.asy
+++ b/CMOS/clamp_up.asy
@@ -1,20 +1,20 @@
-Version 4
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-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 1 48 Center 0 MAX
-TEXT -63 80 Left 0 0
-SYMATTR Description CLAMP UP gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 1 48 Center 0 MAX
+TEXT -63 80 Left 0 0
+SYMATTR Description CLAMP UP gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/consensus.asc b/CMOS/consensus.asc
index 15d3dc6..9da0552 100644
--- a/CMOS/consensus.asc
+++ b/CMOS/consensus.asc
@@ -1,15 +1,15 @@
-Version 4
-SHEET 1 880 680
-WIRE 32 144 16 144
-WIRE 272 160 256 160
-WIRE 32 176 16 176
-FLAG 16 144 A
-IOPIN 16 144 In
-FLAG 16 176 B
-IOPIN 16 176 In
-FLAG 272 160 Y
-IOPIN 272 160 Out
-SYMBOL .\\inverting_consensus 80 96 R0
-SYMATTR InstName U1
-SYMBOL .\\standard_inverter 192 112 R0
-SYMATTR InstName U2
+Version 4
+SHEET 1 880 680
+WIRE 32 144 16 144
+WIRE 272 160 256 160
+WIRE 32 176 16 176
+FLAG 16 144 A
+IOPIN 16 144 In
+FLAG 16 176 B
+IOPIN 16 176 In
+FLAG 272 160 Y
+IOPIN 272 160 Out
+SYMBOL .\\inverting_consensus 80 96 R0
+SYMATTR InstName U1
+SYMBOL .\\standard_inverter 192 112 R0
+SYMATTR InstName U2
diff --git a/CMOS/consensus.asy b/CMOS/consensus.asy
index 1201fa4..b7aff7d 100644
--- a/CMOS/consensus.asy
+++ b/CMOS/consensus.asy
@@ -1,22 +1,22 @@
-Version 4
-SymbolType CELL
-LINE Normal 48 64 32 64
-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 0 52 Center 0 CON
-SYMATTR Description 2-input consensus gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 0 52 Center 0 CON
+SYMATTR Description 2-input consensus gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/custom.mos b/CMOS/custom.mos
index 9f38457..d63d327 100644
--- a/CMOS/custom.mos
+++ b/CMOS/custom.mos
@@ -1,24 +1,24 @@
-.model P-DEP VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
-
-.model N-DEP VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
-
-
-
-.model P-DLOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
-
-.model N-DLOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
-
-
-
-
-
-
-.model P-ENH VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
-
-.model N-ENH VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
-
-
-
-.model P-ELOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
-
+.model P-DEP VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
+
+.model N-DEP VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
+
+
+
+.model P-DLOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
+
+.model N-DLOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=-0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
+
+
+
+
+
+
+.model P-ENH VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-1.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
+
+.model N-ENH VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=1.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
+
+
+
+.model P-ELOW VDMOS(pchan Rg=3 Rd=14m Rs=10m Vto=-0.5 Kp=32 Cgdmax=.5n Cgdmin=.07n Cgs=.9n Cjo=.26n Is=26p Rb=17m mfg=Custom Vds=-20 Ron=34m Qg=13n)
+
 .model N-ELOW VDMOS(Rg=3 Rd=4.8m Rs=3.6m Vto=0.5 Kp=90 Cgdmax=.7n Cgdmin=.25n Cgs=1n Cjo=.36n Is=36p Rb=6m mfg=Custom Vds=20 Ron=12m Qg=18n)
 \ No newline at end of file
diff --git a/CMOS/decrement.asc b/CMOS/decrement.asc
index e38789b..9ed740e 100644
--- a/CMOS/decrement.asc
+++ b/CMOS/decrement.asc
@@ -1,73 +1,73 @@
-Version 4
-SHEET 1 880 680
-WIRE -336 -192 -400 -192
-WIRE 144 -192 -256 -192
-WIRE -400 -160 -400 -192
-WIRE 144 -144 144 -192
-WIRE 96 -128 16 -128
-WIRE 144 -16 144 -48
-WIRE 672 -16 144 -16
-WIRE 768 -16 672 -16
-WIRE 144 32 144 -16
-WIRE 16 48 16 -128
-WIRE 16 48 -256 48
-WIRE 16 112 16 48
-WIRE 96 112 16 112
-WIRE 144 160 144 128
-WIRE 672 208 672 -16
-WIRE 480 240 192 240
-WIRE 144 288 144 256
-WIRE 624 288 560 288
-WIRE 16 352 16 112
-WIRE 272 352 16 352
-WIRE 560 352 560 288
-WIRE 560 352 272 352
-WIRE 672 368 672 304
-WIRE 272 448 272 352
-WIRE 320 448 272 448
-WIRE 480 448 480 240
-WIRE 480 448 432 448
-WIRE 624 448 480 448
-WIRE -336 512 -400 512
-WIRE 672 512 672 464
-WIRE 672 512 -256 512
-WIRE -400 544 -400 512
-FLAG -400 -160 0
-FLAG 144 288 0
-FLAG -400 544 0
-FLAG -256 48 A
-IOPIN -256 48 In
-FLAG 768 -16 Y
-IOPIN 768 -16 Out
-SYMBOL nmos 96 32 R0
-SYMATTR InstName M1
-SYMATTR Value N-ELOW
-SYMBOL pmos 192 160 M0
-SYMATTR InstName M2
-SYMATTR Value P-DLOW
-SYMBOL pmos 96 -48 M180
-SYMATTR InstName M3
-SYMATTR Value P-ENH
-SYMBOL voltage -240 -192 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V1
-SYMATTR Value 1
-SYMBOL voltage -240 512 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V3
-SYMATTR Value -1
-SYMBOL nmos 624 208 R0
-SYMATTR InstName M6
-SYMATTR Value N-ELOW
-SYMBOL nmos 624 368 R0
-SYMATTR InstName M7
-SYMATTR Value N-ENH
-SYMBOL .\\positive_threshold_inverter 368 400 R0
-SYMATTR InstName U1
-TEXT 536 -184 Left 0 !.inc ./custom.mos
+Version 4
+SHEET 1 880 680
+WIRE -336 -192 -400 -192
+WIRE 144 -192 -256 -192
+WIRE -400 -160 -400 -192
+WIRE 144 -144 144 -192
+WIRE 96 -128 16 -128
+WIRE 144 -16 144 -48
+WIRE 672 -16 144 -16
+WIRE 768 -16 672 -16
+WIRE 144 32 144 -16
+WIRE 16 48 16 -128
+WIRE 16 48 -256 48
+WIRE 16 112 16 48
+WIRE 96 112 16 112
+WIRE 144 160 144 128
+WIRE 672 208 672 -16
+WIRE 480 240 192 240
+WIRE 144 288 144 256
+WIRE 624 288 560 288
+WIRE 16 352 16 112
+WIRE 272 352 16 352
+WIRE 560 352 560 288
+WIRE 560 352 272 352
+WIRE 672 368 672 304
+WIRE 272 448 272 352
+WIRE 320 448 272 448
+WIRE 480 448 480 240
+WIRE 480 448 432 448
+WIRE 624 448 480 448
+WIRE -336 512 -400 512
+WIRE 672 512 672 464
+WIRE 672 512 -256 512
+WIRE -400 544 -400 512
+FLAG -400 -160 0
+FLAG 144 288 0
+FLAG -400 544 0
+FLAG -256 48 A
+IOPIN -256 48 In
+FLAG 768 -16 Y
+IOPIN 768 -16 Out
+SYMBOL nmos 96 32 R0
+SYMATTR InstName M1
+SYMATTR Value N-ELOW
+SYMBOL pmos 192 160 M0
+SYMATTR InstName M2
+SYMATTR Value P-DLOW
+SYMBOL pmos 96 -48 M180
+SYMATTR InstName M3
+SYMATTR Value P-ENH
+SYMBOL voltage -240 -192 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -240 512 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value -1
+SYMBOL nmos 624 208 R0
+SYMATTR InstName M6
+SYMATTR Value N-ELOW
+SYMBOL nmos 624 368 R0
+SYMATTR InstName M7
+SYMATTR Value N-ENH
+SYMBOL .\\positive_threshold_inverter 368 400 R0
+SYMATTR InstName U1
+TEXT 536 -184 Left 0 !.inc ./custom.mos
diff --git a/CMOS/decrement.asy b/CMOS/decrement.asy
index 3e3d8f7..4d5540b 100644
--- a/CMOS/decrement.asy
+++ b/CMOS/decrement.asy
@@ -1,17 +1,17 @@
-Version 4
-SymbolType CELL
-LINE Normal 32 48 64 48
-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-TEXT 0 48 Center 0 -1
-SYMATTR Description Decrement gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+TEXT 0 48 Center 0 -1
+SYMATTR Description Decrement gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 2
diff --git a/CMOS/equality.asc b/CMOS/equality.asc
index 58bc12c..4cfc348 100644
--- a/CMOS/equality.asc
+++ b/CMOS/equality.asc
@@ -1,169 +1,169 @@
-Version 4
-SHEET 1 944 868
-WIRE -400 -240 -448 -240
-WIRE -128 -240 -320 -240
-WIRE 128 -240 -128 -240
-WIRE 704 -240 128 -240
-WIRE -448 -208 -448 -240
-WIRE 448 -176 224 -176
-WIRE -128 -128 -128 -240
-WIRE 128 -128 128 -240
-WIRE 448 -128 448 -176
-WIRE 704 -128 704 -240
-WIRE -224 -112 -592 -112
-WIRE -176 -112 -224 -112
-WIRE 80 -112 32 -112
-WIRE 400 -112 288 -112
-WIRE 656 -112 560 -112
-WIRE -224 -16 -224 -112
-WIRE 32 -16 32 -112
-WIRE 32 -16 -224 -16
-WIRE -592 48 -592 -112
-WIRE -592 48 -784 48
-WIRE -544 48 -592 48
-WIRE 288 48 288 -112
-WIRE 288 48 -432 48
-WIRE 560 48 560 -112
-WIRE 560 48 288 48
-WIRE -128 64 -128 -32
-WIRE 128 64 128 -32
-WIRE 448 64 448 -32
-WIRE 704 64 704 -32
-WIRE -176 80 -288 80
-WIRE 80 80 -32 80
-WIRE 400 80 352 80
-WIRE 656 80 608 80
-WIRE 352 176 352 80
-WIRE 352 176 -384 176
-WIRE 608 176 608 80
-WIRE 608 176 352 176
-WIRE 128 208 128 160
-WIRE 224 208 224 -176
-WIRE 224 208 128 208
-WIRE -128 272 -128 160
-WIRE 128 272 -128 272
-WIRE 448 272 448 160
-WIRE 448 272 128 272
-WIRE 704 272 704 160
-WIRE 704 272 448 272
-WIRE 864 272 704 272
-WIRE -592 352 -784 352
-WIRE -544 352 -592 352
-WIRE -384 352 -384 176
-WIRE -384 352 -432 352
-WIRE -128 384 -128 272
-WIRE 128 384 128 272
-WIRE 448 384 448 272
-WIRE 704 384 704 272
-WIRE -224 464 -224 -16
-WIRE -176 464 -224 464
-WIRE 32 464 32 -16
-WIRE 80 464 32 464
-WIRE 288 464 288 48
-WIRE 400 464 288 464
-WIRE 560 464 560 48
-WIRE 656 464 560 464
-WIRE -592 512 -592 352
-WIRE -288 512 -288 80
-WIRE -288 512 -592 512
-WIRE -32 512 -32 80
-WIRE -32 512 -288 512
-WIRE 352 512 -32 512
-WIRE 608 512 352 512
-WIRE -384 560 -384 352
-WIRE 32 560 -384 560
-WIRE -128 576 -128 480
-WIRE 128 576 128 480
-WIRE 448 576 448 480
-WIRE 704 576 704 480
-WIRE -384 656 -384 560
-WIRE -176 656 -384 656
-WIRE 32 656 32 560
-WIRE 80 656 32 656
-WIRE 352 656 352 512
-WIRE 400 656 352 656
-WIRE 608 656 608 512
-WIRE 656 656 608 656
-WIRE -400 784 -448 784
-WIRE -128 784 -128 672
-WIRE -128 784 -320 784
-WIRE 128 784 128 672
-WIRE 128 784 -128 784
-WIRE 448 784 448 672
-WIRE 448 784 128 784
-WIRE 704 784 704 672
-WIRE 704 784 448 784
-WIRE -448 816 -448 784
-FLAG -448 816 0
-FLAG -448 -208 0
-FLAG -784 48 A
-IOPIN -784 48 In
-FLAG -784 352 B
-IOPIN -784 352 In
-FLAG 864 272 Y
-IOPIN 864 272 Out
-SYMBOL pmos -176 -32 M180
-SYMATTR InstName M1
-SYMATTR Value P-ENH
-SYMBOL pmos -176 160 M180
-SYMATTR InstName M2
-SYMATTR Value P-ENH
-SYMBOL pmos 80 -32 M180
-SYMATTR InstName M3
-SYMATTR Value P-ELOW
-SYMBOL pmos 80 160 M180
-SYMATTR InstName M4
-SYMATTR Value P-ELOW
-SYMBOL pmos 400 -32 M180
-SYMATTR InstName M5
-SYMATTR Value P-ELOW
-SYMBOL pmos 400 160 M180
-SYMATTR InstName M6
-SYMATTR Value P-ELOW
-SYMBOL pmos 656 -32 M180
-SYMATTR InstName M7
-SYMATTR Value P-ENH
-SYMBOL pmos 656 160 M180
-SYMATTR InstName M8
-SYMATTR Value P-ENH
-SYMBOL voltage -304 -240 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-SYMATTR InstName V1
-SYMATTR Value 1
-SYMBOL nmos -176 384 R0
-SYMATTR InstName M9
-SYMATTR Value N-ENH
-SYMBOL nmos -176 576 R0
-SYMATTR InstName M10
-SYMATTR Value N-ELOW
-SYMBOL nmos 80 384 R0
-SYMATTR InstName M11
-SYMATTR Value N-ELOW
-SYMBOL nmos 80 576 R0
-SYMATTR InstName M12
-SYMATTR Value N-ENH
-SYMBOL nmos 400 384 R0
-SYMATTR InstName M13
-SYMATTR Value N-ENH
-SYMBOL nmos 400 576 R0
-SYMATTR InstName M14
-SYMATTR Value N-ELOW
-SYMBOL nmos 656 384 R0
-SYMATTR InstName M15
-SYMATTR Value N-ELOW
-SYMBOL nmos 656 576 R0
-SYMATTR InstName M16
-SYMATTR Value N-ENH
-SYMBOL voltage -304 784 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V2
-SYMATTR Value -1
-SYMBOL .\\standard_inverter -496 0 R0
-SYMATTR InstName U1
-SYMBOL .\\standard_inverter -496 304 R0
-SYMATTR InstName U2
-TEXT -752 624 Left 0 !.inc ./custom.mos
+Version 4
+SHEET 1 944 868
+WIRE -400 -240 -448 -240
+WIRE -128 -240 -320 -240
+WIRE 128 -240 -128 -240
+WIRE 704 -240 128 -240
+WIRE -448 -208 -448 -240
+WIRE 448 -176 224 -176
+WIRE -128 -128 -128 -240
+WIRE 128 -128 128 -240
+WIRE 448 -128 448 -176
+WIRE 704 -128 704 -240
+WIRE -224 -112 -592 -112
+WIRE -176 -112 -224 -112
+WIRE 80 -112 32 -112
+WIRE 400 -112 288 -112
+WIRE 656 -112 560 -112
+WIRE -224 -16 -224 -112
+WIRE 32 -16 32 -112
+WIRE 32 -16 -224 -16
+WIRE -592 48 -592 -112
+WIRE -592 48 -784 48
+WIRE -544 48 -592 48
+WIRE 288 48 288 -112
+WIRE 288 48 -432 48
+WIRE 560 48 560 -112
+WIRE 560 48 288 48
+WIRE -128 64 -128 -32
+WIRE 128 64 128 -32
+WIRE 448 64 448 -32
+WIRE 704 64 704 -32
+WIRE -176 80 -288 80
+WIRE 80 80 -32 80
+WIRE 400 80 352 80
+WIRE 656 80 608 80
+WIRE 352 176 352 80
+WIRE 352 176 -384 176
+WIRE 608 176 608 80
+WIRE 608 176 352 176
+WIRE 128 208 128 160
+WIRE 224 208 224 -176
+WIRE 224 208 128 208
+WIRE -128 272 -128 160
+WIRE 128 272 -128 272
+WIRE 448 272 448 160
+WIRE 448 272 128 272
+WIRE 704 272 704 160
+WIRE 704 272 448 272
+WIRE 864 272 704 272
+WIRE -592 352 -784 352
+WIRE -544 352 -592 352
+WIRE -384 352 -384 176
+WIRE -384 352 -432 352
+WIRE -128 384 -128 272
+WIRE 128 384 128 272
+WIRE 448 384 448 272
+WIRE 704 384 704 272
+WIRE -224 464 -224 -16
+WIRE -176 464 -224 464
+WIRE 32 464 32 -16
+WIRE 80 464 32 464
+WIRE 288 464 288 48
+WIRE 400 464 288 464
+WIRE 560 464 560 48
+WIRE 656 464 560 464
+WIRE -592 512 -592 352
+WIRE -288 512 -288 80
+WIRE -288 512 -592 512
+WIRE -32 512 -32 80
+WIRE -32 512 -288 512
+WIRE 352 512 -32 512
+WIRE 608 512 352 512
+WIRE -384 560 -384 352
+WIRE 32 560 -384 560
+WIRE -128 576 -128 480
+WIRE 128 576 128 480
+WIRE 448 576 448 480
+WIRE 704 576 704 480
+WIRE -384 656 -384 560
+WIRE -176 656 -384 656
+WIRE 32 656 32 560
+WIRE 80 656 32 656
+WIRE 352 656 352 512
+WIRE 400 656 352 656
+WIRE 608 656 608 512
+WIRE 656 656 608 656
+WIRE -400 784 -448 784
+WIRE -128 784 -128 672
+WIRE -128 784 -320 784
+WIRE 128 784 128 672
+WIRE 128 784 -128 784
+WIRE 448 784 448 672
+WIRE 448 784 128 784
+WIRE 704 784 704 672
+WIRE 704 784 448 784
+WIRE -448 816 -448 784
+FLAG -448 816 0
+FLAG -448 -208 0
+FLAG -784 48 A
+IOPIN -784 48 In
+FLAG -784 352 B
+IOPIN -784 352 In
+FLAG 864 272 Y
+IOPIN 864 272 Out
+SYMBOL pmos -176 -32 M180
+SYMATTR InstName M1
+SYMATTR Value P-ENH
+SYMBOL pmos -176 160 M180
+SYMATTR InstName M2
+SYMATTR Value P-ENH
+SYMBOL pmos 80 -32 M180
+SYMATTR InstName M3
+SYMATTR Value P-ELOW
+SYMBOL pmos 80 160 M180
+SYMATTR InstName M4
+SYMATTR Value P-ELOW
+SYMBOL pmos 400 -32 M180
+SYMATTR InstName M5
+SYMATTR Value P-ELOW
+SYMBOL pmos 400 160 M180
+SYMATTR InstName M6
+SYMATTR Value P-ELOW
+SYMBOL pmos 656 -32 M180
+SYMATTR InstName M7
+SYMATTR Value P-ENH
+SYMBOL pmos 656 160 M180
+SYMATTR InstName M8
+SYMATTR Value P-ENH
+SYMBOL voltage -304 -240 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL nmos -176 384 R0
+SYMATTR InstName M9
+SYMATTR Value N-ENH
+SYMBOL nmos -176 576 R0
+SYMATTR InstName M10
+SYMATTR Value N-ELOW
+SYMBOL nmos 80 384 R0
+SYMATTR InstName M11
+SYMATTR Value N-ELOW
+SYMBOL nmos 80 576 R0
+SYMATTR InstName M12
+SYMATTR Value N-ENH
+SYMBOL nmos 400 384 R0
+SYMATTR InstName M13
+SYMATTR Value N-ENH
+SYMBOL nmos 400 576 R0
+SYMATTR InstName M14
+SYMATTR Value N-ELOW
+SYMBOL nmos 656 384 R0
+SYMATTR InstName M15
+SYMATTR Value N-ELOW
+SYMBOL nmos 656 576 R0
+SYMATTR InstName M16
+SYMATTR Value N-ENH
+SYMBOL voltage -304 784 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value -1
+SYMBOL .\\standard_inverter -496 0 R0
+SYMATTR InstName U1
+SYMBOL .\\standard_inverter -496 304 R0
+SYMATTR InstName U2
+TEXT -752 624 Left 0 !.inc ./custom.mos
diff --git a/CMOS/equality.asy b/CMOS/equality.asy
index c6470ce..14fb10a 100644
--- a/CMOS/equality.asy
+++ b/CMOS/equality.asy
@@ -1,22 +1,22 @@
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-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 0 52 Center 0 =
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-PIN -48 48 NONE 0
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-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
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+LINE Normal -32 96 32 96
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+TEXT 0 52 Center 0 =
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+PIN -48 48 NONE 0
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+PINATTR PinName B
+PINATTR SpiceOrder 2
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diff --git a/CMOS/gullible.asc b/CMOS/gullible.asc
index ab6240d..dccd112 100644
--- a/CMOS/gullible.asc
+++ b/CMOS/gullible.asc
@@ -1,15 +1,15 @@
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-SYMATTR InstName U1
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-SYMATTR InstName U2
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+SYMATTR InstName U1
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diff --git a/CMOS/gullible.asy b/CMOS/gullible.asy
index cd75b7e..7d8ba23 100644
--- a/CMOS/gullible.asy
+++ b/CMOS/gullible.asy
@@ -1,22 +1,22 @@
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-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 0 52 Center 0 GUL
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-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
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+TEXT 0 52 Center 0 GUL
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+PINATTR SpiceOrder 3
diff --git a/CMOS/increment.asc b/CMOS/increment.asc
index 533c432..7a09449 100644
--- a/CMOS/increment.asc
+++ b/CMOS/increment.asc
@@ -1,73 +1,73 @@
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-SYMATTR InstName M7
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+SYMATTR InstName U1
+TEXT 296 472 Left 0 !.inc ./custom.mos
diff --git a/CMOS/increment.asy b/CMOS/increment.asy
index b4f6f39..0d06e22 100644
--- a/CMOS/increment.asy
+++ b/CMOS/increment.asy
@@ -1,17 +1,17 @@
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-SYMATTR Description Increment gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
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+TEXT 0 48 Center 0 +1
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diff --git a/CMOS/inverting_consensus.asc b/CMOS/inverting_consensus.asc
index ef326e8..01357f4 100644
--- a/CMOS/inverting_consensus.asc
+++ b/CMOS/inverting_consensus.asc
@@ -1,100 +1,100 @@
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diff --git a/CMOS/inverting_consensus.asy b/CMOS/inverting_consensus.asy
index c0f87df..54f5aca 100644
--- a/CMOS/inverting_consensus.asy
+++ b/CMOS/inverting_consensus.asy
@@ -1,23 +1,23 @@
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-LINE Normal -32 32 -32 96
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-PINATTR SpiceOrder 1
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-PINATTR PinName B
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diff --git a/CMOS/inverting_gullible.asc b/CMOS/inverting_gullible.asc
index 8a4888c..26a542e 100644
--- a/CMOS/inverting_gullible.asc
+++ b/CMOS/inverting_gullible.asc
@@ -1,162 +1,162 @@
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+WIRE -80 48 -80 -48
+WIRE 176 48 176 -48
+WIRE -176 64 -176 32
+WIRE -176 64 -352 64
+WIRE -128 64 -176 64
+WIRE 32 64 32 32
+WIRE 128 64 32 64
+WIRE 336 96 336 -32
+WIRE 624 96 336 96
+WIRE 816 96 816 0
+WIRE 816 96 624 96
+WIRE 464 112 464 16
+WIRE 720 112 720 16
+WIRE 976 112 976 16
+WIRE 384 192 384 32
+WIRE 416 192 384 192
+WIRE 624 192 624 96
+WIRE 672 192 624 192
+WIRE 880 192 880 32
+WIRE 928 192 880 192
+WIRE -80 208 -80 144
+WIRE 176 208 176 144
+WIRE 176 208 -80 208
+WIRE 288 208 288 -160
+WIRE 288 208 176 208
+WIRE -80 272 -80 208
+WIRE 176 272 176 208
+WIRE 720 272 720 208
+WIRE 976 272 976 208
+WIRE 976 272 720 272
+WIRE 464 304 464 208
+WIRE 976 336 976 272
+WIRE -240 352 -240 -128
+WIRE -240 352 -352 352
+WIRE -128 352 -240 352
+WIRE 128 352 80 352
+WIRE 336 384 336 96
+WIRE 416 384 336 384
+WIRE -240 400 -240 352
+WIRE 80 400 80 352
+WIRE 80 400 -240 400
+WIRE -80 464 -80 368
+WIRE 176 464 176 368
+WIRE 464 496 464 400
+WIRE -176 544 -176 64
+WIRE -128 544 -176 544
+WIRE 32 544 32 64
+WIRE 128 544 32 544
+WIRE 336 576 336 384
+WIRE 416 576 336 576
+WIRE -352 624 -384 624
+WIRE -80 624 -80 560
+WIRE -80 624 -272 624
+WIRE 176 624 176 560
+WIRE 176 624 -80 624
+WIRE 464 624 464 592
+WIRE 720 624 720 272
+WIRE 720 624 464 624
+WIRE -384 656 -384 624
+FLAG -384 656 0
+FLAG 976 336 0
+FLAG -384 -176 0
+FLAG -352 64 A
+IOPIN -352 64 In
+FLAG -352 352 B
+IOPIN -352 352 In
+FLAG 1088 -160 Y
+IOPIN 1088 -160 Out
+SYMBOL pmos -128 -48 M180
+SYMATTR InstName M1
+SYMATTR Value P-ENH
+SYMBOL pmos -128 144 M180
+SYMATTR InstName M2
+SYMATTR Value P-ELOW
+SYMBOL pmos 128 -48 M180
+SYMATTR InstName M3
+SYMATTR Value P-ELOW
+SYMBOL pmos 128 144 M180
+SYMATTR InstName M4
+SYMATTR Value P-ENH
+SYMBOL nmos -128 272 R0
+SYMATTR InstName M5
+SYMATTR Value N-ELOW
+SYMBOL nmos -128 464 R0
+SYMATTR InstName M6
+SYMATTR Value N-ENH
+SYMBOL nmos 128 272 R0
+SYMATTR InstName M7
+SYMATTR Value N-ENH
+SYMBOL nmos 128 464 R0
+SYMATTR InstName M8
+SYMATTR Value N-ELOW
+SYMBOL voltage -256 -208 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -256 624 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value -1
+SYMBOL nmos 416 -80 R0
+SYMATTR InstName M9
+SYMATTR Value N-DLOW
+SYMBOL nmos 672 -80 R0
+SYMATTR InstName M10
+SYMATTR Value N-ELOW
+SYMBOL nmos 928 -80 R0
+SYMATTR InstName M11
+SYMATTR Value N-ELOW
+SYMBOL pmos 416 112 R0
+SYMATTR InstName M12
+SYMATTR Value P-DLOW
+SYMBOL pmos 672 112 R0
+SYMATTR InstName M13
+SYMATTR Value P-ELOW
+SYMBOL pmos 928 112 R0
+SYMATTR InstName M14
+SYMATTR Value P-ELOW
+SYMBOL nmos 416 304 R0
+SYMATTR InstName M15
+SYMATTR Value N-DLOW
+SYMBOL pmos 416 496 R0
+SYMATTR InstName M16
+SYMATTR Value P-DLOW
+TEXT 280 -272 Left 0 !.inc ./custom.mos
diff --git a/CMOS/inverting_gullible.asy b/CMOS/inverting_gullible.asy
index 3e6991f..34a9c84 100644
--- a/CMOS/inverting_gullible.asy
+++ b/CMOS/inverting_gullible.asy
@@ -1,23 +1,23 @@
-Version 4
-SymbolType CELL
-LINE Normal 48 64 32 64
-LINE Normal 32 56 48 64
-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 0 52 Center 0 GUL
-SYMATTR Description 2-input inverting gullible
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 56 48 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 0 52 Center 0 GUL
+SYMATTR Description 2-input inverting gullible
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/is_false.asc b/CMOS/is_false.asc
index 44db15a..c02d271 100644
--- a/CMOS/is_false.asc
+++ b/CMOS/is_false.asc
@@ -1,10 +1,10 @@
-Version 4
-SHEET 1 924 680
-WIRE -112 128 -128 128
-WIRE 16 128 0 128
-FLAG -128 128 A
-IOPIN -128 128 In
-FLAG 16 128 Y
-IOPIN 16 128 Out
-SYMBOL .\\negative_threshold_inverter -64 80 R0
-SYMATTR InstName U1
+Version 4
+SHEET 1 924 680
+WIRE -112 128 -128 128
+WIRE 16 128 0 128
+FLAG -128 128 A
+IOPIN -128 128 In
+FLAG 16 128 Y
+IOPIN 16 128 Out
+SYMBOL .\\negative_threshold_inverter -64 80 R0
+SYMATTR InstName U1
diff --git a/CMOS/is_false.asy b/CMOS/is_false.asy
index e5e3fee..2204505 100644
--- a/CMOS/is_false.asy
+++ b/CMOS/is_false.asy
@@ -1,17 +1,17 @@
-Version 4
-SymbolType CELL
-LINE Normal 32 48 64 48
-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-TEXT 0 48 Center 0 =-
-SYMATTR Description IS FALSE gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+TEXT 0 48 Center 0 =-
+SYMATTR Description IS FALSE gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 2
diff --git a/CMOS/is_true.asc b/CMOS/is_true.asc
index 37700f7..199c42a 100644
--- a/CMOS/is_true.asc
+++ b/CMOS/is_true.asc
@@ -1,12 +1,12 @@
-Version 4
-SHEET 1 924 680
-WIRE -16 96 -32 96
-WIRE 224 96 208 96
-FLAG -32 96 A
-IOPIN -32 96 In
-FLAG 224 96 Y
-IOPIN 224 96 Out
-SYMBOL .\\positive_threshold_inverter 32 48 R0
-SYMATTR InstName U1
-SYMBOL .\\negative_threshold_inverter 144 48 R0
-SYMATTR InstName U2
+Version 4
+SHEET 1 924 680
+WIRE -16 96 -32 96
+WIRE 224 96 208 96
+FLAG -32 96 A
+IOPIN -32 96 In
+FLAG 224 96 Y
+IOPIN 224 96 Out
+SYMBOL .\\positive_threshold_inverter 32 48 R0
+SYMATTR InstName U1
+SYMBOL .\\negative_threshold_inverter 144 48 R0
+SYMATTR InstName U2
diff --git a/CMOS/is_true.asy b/CMOS/is_true.asy
index 5105d90..0edb8b6 100644
--- a/CMOS/is_true.asy
+++ b/CMOS/is_true.asy
@@ -1,17 +1,17 @@
-Version 4
-SymbolType CELL
-LINE Normal 32 48 64 48
-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-TEXT 0 48 Center 0 =+
-SYMATTR Description IS TRUE gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+TEXT 0 48 Center 0 =+
+SYMATTR Description IS TRUE gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 2
diff --git a/CMOS/is_unknown.asc b/CMOS/is_unknown.asc
index efe88fe..4789591 100644
--- a/CMOS/is_unknown.asc
+++ b/CMOS/is_unknown.asc
@@ -1,67 +1,67 @@
-Version 4
-SHEET 1 956 680
-WIRE -288 -192 -336 -192
-WIRE 304 -192 -208 -192
-WIRE -336 -160 -336 -192
-WIRE 304 -160 304 -192
-WIRE 256 -144 112 -144
-WIRE 304 -32 304 -64
-WIRE 256 -16 192 -16
-WIRE -112 96 -208 96
-WIRE -48 96 -112 96
-WIRE 192 96 192 -16
-WIRE 192 96 64 96
-WIRE 304 96 304 64
-WIRE 544 96 304 96
-WIRE 656 96 544 96
-WIRE -112 176 -112 96
-WIRE 112 176 112 -144
-WIRE 112 176 -112 176
-WIRE 432 176 112 176
-WIRE 304 240 304 96
-WIRE 544 240 544 96
-WIRE 192 320 192 96
-WIRE 256 320 192 320
-WIRE 432 320 432 176
-WIRE 496 320 432 320
-WIRE -288 400 -336 400
-WIRE 304 400 304 336
-WIRE 304 400 -208 400
-WIRE 544 400 544 336
-WIRE 544 400 304 400
-WIRE -336 432 -336 400
-FLAG -336 -160 0
-FLAG -336 432 0
-FLAG -208 96 A
-IOPIN -208 96 In
-FLAG 656 96 Y
-IOPIN 656 96 Out
-SYMBOL voltage -192 -192 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V1
-SYMATTR Value 1
-SYMBOL voltage -192 400 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V3
-SYMATTR Value -1
-SYMBOL nmos 256 240 R0
-SYMATTR InstName M3
-SYMATTR Value N-ELOW
-SYMBOL nmos 496 240 R0
-SYMATTR InstName M4
-SYMATTR Value N-ENH
-SYMBOL pmos 256 64 M180
-SYMATTR InstName M5
-SYMATTR Value P-ENH
-SYMBOL pmos 256 -64 M180
-SYMATTR InstName M6
-SYMATTR Value P-ELOW
-SYMBOL .\\negative_threshold_inverter 0 48 R0
-SYMATTR InstName U1
-TEXT 360 -208 Left 0 !.inc ./custom.mos
+Version 4
+SHEET 1 956 680
+WIRE -288 -192 -336 -192
+WIRE 304 -192 -208 -192
+WIRE -336 -160 -336 -192
+WIRE 304 -160 304 -192
+WIRE 256 -144 112 -144
+WIRE 304 -32 304 -64
+WIRE 256 -16 192 -16
+WIRE -112 96 -208 96
+WIRE -48 96 -112 96
+WIRE 192 96 192 -16
+WIRE 192 96 64 96
+WIRE 304 96 304 64
+WIRE 544 96 304 96
+WIRE 656 96 544 96
+WIRE -112 176 -112 96
+WIRE 112 176 112 -144
+WIRE 112 176 -112 176
+WIRE 432 176 112 176
+WIRE 304 240 304 96
+WIRE 544 240 544 96
+WIRE 192 320 192 96
+WIRE 256 320 192 320
+WIRE 432 320 432 176
+WIRE 496 320 432 320
+WIRE -288 400 -336 400
+WIRE 304 400 304 336
+WIRE 304 400 -208 400
+WIRE 544 400 544 336
+WIRE 544 400 304 400
+WIRE -336 432 -336 400
+FLAG -336 -160 0
+FLAG -336 432 0
+FLAG -208 96 A
+IOPIN -208 96 In
+FLAG 656 96 Y
+IOPIN 656 96 Out
+SYMBOL voltage -192 -192 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -192 400 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value -1
+SYMBOL nmos 256 240 R0
+SYMATTR InstName M3
+SYMATTR Value N-ELOW
+SYMBOL nmos 496 240 R0
+SYMATTR InstName M4
+SYMATTR Value N-ENH
+SYMBOL pmos 256 64 M180
+SYMATTR InstName M5
+SYMATTR Value P-ENH
+SYMBOL pmos 256 -64 M180
+SYMATTR InstName M6
+SYMATTR Value P-ELOW
+SYMBOL .\\negative_threshold_inverter 0 48 R0
+SYMATTR InstName U1
+TEXT 360 -208 Left 0 !.inc ./custom.mos
diff --git a/CMOS/is_unknown.asy b/CMOS/is_unknown.asy
index 8ffb820..49da4de 100644
--- a/CMOS/is_unknown.asy
+++ b/CMOS/is_unknown.asy
@@ -1,17 +1,17 @@
-Version 4
-SymbolType CELL
-LINE Normal 32 48 64 48
-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-TEXT 0 48 Center 0 =0
-SYMATTR Description IS UNKNOWN gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+TEXT 0 48 Center 0 =0
+SYMATTR Description IS UNKNOWN gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 2
diff --git a/CMOS/monadic_decoder.asc b/CMOS/monadic_decoder.asc
index 5791a49..7b5079e 100644
--- a/CMOS/monadic_decoder.asc
+++ b/CMOS/monadic_decoder.asc
@@ -1,80 +1,80 @@
-Version 4
-SHEET 1 880 680
-WIRE -48 -144 -112 -144
-WIRE 224 -144 64 -144
-WIRE 288 -144 224 -144
-WIRE 64 -64 32 -64
-WIRE 336 -64 144 -64
-WIRE 32 -32 32 -64
-WIRE 336 -32 336 -64
-WIRE 288 -16 160 -16
-WIRE -112 32 -112 -144
-WIRE -112 32 -224 32
-WIRE 336 80 336 64
-WIRE 224 96 224 -144
-WIRE 288 96 224 96
-WIRE 336 208 336 176
-WIRE 576 208 336 208
-WIRE 720 208 576 208
-WIRE -112 240 -112 32
-WIRE 160 240 160 -16
-WIRE 160 240 -112 240
-WIRE 464 240 160 240
-WIRE 336 272 336 208
-WIRE 576 272 576 208
-WIRE 224 352 224 96
-WIRE 288 352 224 352
-WIRE 464 352 464 240
-WIRE 528 352 464 352
-WIRE 64 400 32 400
-WIRE 336 400 336 368
-WIRE 336 400 144 400
-WIRE 576 400 576 368
-WIRE 576 400 336 400
-WIRE 32 432 32 400
-WIRE -112 496 -112 240
-WIRE -48 496 -112 496
-WIRE 288 496 176 496
-FLAG -224 32 A
-IOPIN -224 32 In
-FLAG 288 -144 Y1
-IOPIN 288 -144 Out
-FLAG 288 496 Y3
-IOPIN 288 496 Out
-FLAG 32 -32 0
-FLAG 32 432 0
-FLAG 720 208 Y2
-IOPIN 720 208 Out
-SYMBOL .\\negative_threshold_inverter 0 -192 R0
-SYMATTR InstName U1
-SYMBOL .\\positive_threshold_inverter 0 448 R0
-SYMATTR InstName U2
-SYMBOL .\\negative_threshold_inverter 112 448 R0
-SYMATTR InstName U3
-SYMBOL voltage 160 -64 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V1
-SYMATTR Value 1
-SYMBOL voltage 160 400 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V2
-SYMATTR Value -1
-SYMBOL pmos 288 64 M180
-SYMATTR InstName M1
-SYMATTR Value P-ELOW
-SYMBOL pmos 288 176 M180
-SYMATTR InstName M2
-SYMATTR Value P-ENH
-SYMBOL nmos 288 272 R0
-SYMATTR InstName M3
-SYMATTR Value N-ELOW
-SYMBOL nmos 528 272 R0
-SYMATTR InstName M4
-SYMATTR Value N-ENH
-TEXT 496 -120 Left 0 !.inc ./custom.mos
+Version 4
+SHEET 1 880 680
+WIRE -48 -144 -112 -144
+WIRE 224 -144 64 -144
+WIRE 288 -144 224 -144
+WIRE 64 -64 32 -64
+WIRE 336 -64 144 -64
+WIRE 32 -32 32 -64
+WIRE 336 -32 336 -64
+WIRE 288 -16 160 -16
+WIRE -112 32 -112 -144
+WIRE -112 32 -224 32
+WIRE 336 80 336 64
+WIRE 224 96 224 -144
+WIRE 288 96 224 96
+WIRE 336 208 336 176
+WIRE 576 208 336 208
+WIRE 720 208 576 208
+WIRE -112 240 -112 32
+WIRE 160 240 160 -16
+WIRE 160 240 -112 240
+WIRE 464 240 160 240
+WIRE 336 272 336 208
+WIRE 576 272 576 208
+WIRE 224 352 224 96
+WIRE 288 352 224 352
+WIRE 464 352 464 240
+WIRE 528 352 464 352
+WIRE 64 400 32 400
+WIRE 336 400 336 368
+WIRE 336 400 144 400
+WIRE 576 400 576 368
+WIRE 576 400 336 400
+WIRE 32 432 32 400
+WIRE -112 496 -112 240
+WIRE -48 496 -112 496
+WIRE 288 496 176 496
+FLAG -224 32 A
+IOPIN -224 32 In
+FLAG 288 -144 Y1
+IOPIN 288 -144 Out
+FLAG 288 496 Y3
+IOPIN 288 496 Out
+FLAG 32 -32 0
+FLAG 32 432 0
+FLAG 720 208 Y2
+IOPIN 720 208 Out
+SYMBOL .\\negative_threshold_inverter 0 -192 R0
+SYMATTR InstName U1
+SYMBOL .\\positive_threshold_inverter 0 448 R0
+SYMATTR InstName U2
+SYMBOL .\\negative_threshold_inverter 112 448 R0
+SYMATTR InstName U3
+SYMBOL voltage 160 -64 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage 160 400 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value -1
+SYMBOL pmos 288 64 M180
+SYMATTR InstName M1
+SYMATTR Value P-ELOW
+SYMBOL pmos 288 176 M180
+SYMATTR InstName M2
+SYMATTR Value P-ENH
+SYMBOL nmos 288 272 R0
+SYMATTR InstName M3
+SYMATTR Value N-ELOW
+SYMBOL nmos 528 272 R0
+SYMATTR InstName M4
+SYMATTR Value N-ENH
+TEXT 496 -120 Left 0 !.inc ./custom.mos
diff --git a/CMOS/monadic_decoder.asy b/CMOS/monadic_decoder.asy
index 7e2d830..e4f8037 100644
--- a/CMOS/monadic_decoder.asy
+++ b/CMOS/monadic_decoder.asy
@@ -1,28 +1,28 @@
-Version 4
-SymbolType CELL
-LINE Normal 64 80 32 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 128 32 32
-LINE Normal -32 128 32 128
-LINE Normal -32 32 -32 128
-LINE Normal 64 48 32 48
-LINE Normal 64 112 32 112
-LINE Normal -64 80 -32 80
-TEXT -20 80 Left 0 =
-TEXT 3 46 Left 0 -
-TEXT 9 46 Left 0 -
-TEXT 10 80 Center 0 0
-TEXT 10 112 Center 0 +
-SYMATTR Description Monadic decoder gate
-PIN -64 80 NONE 8
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 8
-PINATTR PinName Y1
-PINATTR SpiceOrder 2
-PIN 64 80 NONE 8
-PINATTR PinName Y2
-PINATTR SpiceOrder 3
-PIN 64 112 NONE 8
-PINATTR PinName Y3
-PINATTR SpiceOrder 4
+Version 4
+SymbolType CELL
+LINE Normal 64 80 32 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 128 32 32
+LINE Normal -32 128 32 128
+LINE Normal -32 32 -32 128
+LINE Normal 64 48 32 48
+LINE Normal 64 112 32 112
+LINE Normal -64 80 -32 80
+TEXT -20 80 Left 0 =
+TEXT 3 46 Left 0 -
+TEXT 9 46 Left 0 -
+TEXT 10 80 Center 0 0
+TEXT 10 112 Center 0 +
+SYMATTR Description Monadic decoder gate
+PIN -64 80 NONE 8
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 8
+PINATTR PinName Y1
+PINATTR SpiceOrder 2
+PIN 64 80 NONE 8
+PINATTR PinName Y2
+PINATTR SpiceOrder 3
+PIN 64 112 NONE 8
+PINATTR PinName Y3
+PINATTR SpiceOrder 4
diff --git a/CMOS/negative_threshold_inverter.asc b/CMOS/negative_threshold_inverter.asc
index 7380e83..981d829 100644
--- a/CMOS/negative_threshold_inverter.asc
+++ b/CMOS/negative_threshold_inverter.asc
@@ -1,45 +1,45 @@
-Version 4
-SHEET 1 924 680
-WIRE -288 -160 -336 -160
-WIRE 96 -160 -208 -160
-WIRE -336 -128 -336 -160
-WIRE 96 -96 96 -160
-WIRE 48 -80 0 -80
-WIRE 0 96 0 -80
-WIRE 0 96 -208 96
-WIRE 96 96 96 0
-WIRE 256 96 96 96
-WIRE 96 240 96 96
-WIRE 0 320 0 96
-WIRE 48 320 0 320
-WIRE -288 400 -336 400
-WIRE 96 400 96 336
-WIRE 96 400 -208 400
-WIRE -336 432 -336 400
-FLAG -336 432 0
-FLAG -336 -128 0
-FLAG -208 96 A
-IOPIN -208 96 In
-FLAG 256 96 Y
-IOPIN 256 96 Out
-SYMBOL pmos 48 0 M180
-SYMATTR InstName M1
-SYMATTR Value P-ENH
-SYMBOL nmos 48 240 R0
-SYMATTR InstName M2
-SYMATTR Value N-ELOW
-SYMBOL voltage -192 -160 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V1
-SYMATTR Value 1
-SYMBOL voltage -192 400 R90
-WINDOW 0 -32 56 VBottom 0
-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V3
-SYMATTR Value -1
-TEXT 408 -160 Left 0 !.inc ./custom.mos
+Version 4
+SHEET 1 924 680
+WIRE -288 -160 -336 -160
+WIRE 96 -160 -208 -160
+WIRE -336 -128 -336 -160
+WIRE 96 -96 96 -160
+WIRE 48 -80 0 -80
+WIRE 0 96 0 -80
+WIRE 0 96 -208 96
+WIRE 96 96 96 0
+WIRE 256 96 96 96
+WIRE 96 240 96 96
+WIRE 0 320 0 96
+WIRE 48 320 0 320
+WIRE -288 400 -336 400
+WIRE 96 400 96 336
+WIRE 96 400 -208 400
+WIRE -336 432 -336 400
+FLAG -336 432 0
+FLAG -336 -128 0
+FLAG -208 96 A
+IOPIN -208 96 In
+FLAG 256 96 Y
+IOPIN 256 96 Out
+SYMBOL pmos 48 0 M180
+SYMATTR InstName M1
+SYMATTR Value P-ENH
+SYMBOL nmos 48 240 R0
+SYMATTR InstName M2
+SYMATTR Value N-ELOW
+SYMBOL voltage -192 -160 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -192 400 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value -1
+TEXT 408 -160 Left 0 !.inc ./custom.mos
diff --git a/CMOS/negative_threshold_inverter.asy b/CMOS/negative_threshold_inverter.asy
index 91e3aad..3e4e735 100644
--- a/CMOS/negative_threshold_inverter.asy
+++ b/CMOS/negative_threshold_inverter.asy
@@ -1,18 +1,18 @@
-Version 4
-SymbolType CELL
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-LINE Normal -32 48 -48 48
-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-LINE Normal 47 48 32 40
-TEXT 0 48 Center 0 NTI
-SYMATTR Description Negative threshold inverter
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
+LINE Normal -32 48 -48 48
+LINE Normal 32 32 -32 32
+LINE Normal 32 64 32 32
+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+TEXT 0 48 Center 0 NTI
+SYMATTR Description Negative threshold inverter
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 2
diff --git a/CMOS/positive_threshold_inverter.asc b/CMOS/positive_threshold_inverter.asc
index 1d0c1c5..25ccd49 100644
--- a/CMOS/positive_threshold_inverter.asc
+++ b/CMOS/positive_threshold_inverter.asc
@@ -1,45 +1,45 @@
-Version 4
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-WIRE -336 -128 -336 -160
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-SYMATTR InstName M2
-SYMATTR Value N-ENH
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-WINDOW 3 32 56 VTop 0
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-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
-SYMATTR InstName V3
-SYMATTR Value -1
-TEXT 408 -160 Left 0 !.inc ./custom.mos
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+SYMATTR InstName M2
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+SYMATTR InstName V1
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+WINDOW 3 32 56 VTop 0
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+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value -1
+TEXT 408 -160 Left 0 !.inc ./custom.mos
diff --git a/CMOS/positive_threshold_inverter.asy b/CMOS/positive_threshold_inverter.asy
index 1122cb4..3ce48e9 100644
--- a/CMOS/positive_threshold_inverter.asy
+++ b/CMOS/positive_threshold_inverter.asy
@@ -1,18 +1,18 @@
-Version 4
-SymbolType CELL
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-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-LINE Normal 47 48 32 40
-TEXT 0 48 Center 0 PTI
-SYMATTR Description Positive threshold inverter
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
+LINE Normal 32 48 64 48
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+LINE Normal -32 64 32 64
+LINE Normal -32 32 -32 64
+LINE Normal 32 40 32 48
+LINE Normal 47 48 32 40
+TEXT 0 48 Center 0 PTI
+SYMATTR Description Positive threshold inverter
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN 64 48 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 2
diff --git a/CMOS/standard_inverter.asc b/CMOS/standard_inverter.asc
index c48a2c7..5f64dd3 100644
--- a/CMOS/standard_inverter.asc
+++ b/CMOS/standard_inverter.asc
@@ -1,63 +1,63 @@
-Version 4
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+WINDOW 39 0 0 Left 0
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+SYMATTR Value -1
+TEXT 408 -160 Left 0 !.inc ./custom.mos
diff --git a/CMOS/standard_inverter.asy b/CMOS/standard_inverter.asy
index fe479d7..4a9c820 100644
--- a/CMOS/standard_inverter.asy
+++ b/CMOS/standard_inverter.asy
@@ -1,18 +1,18 @@
-Version 4
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-LINE Normal 32 32 -32 32
-LINE Normal 32 64 32 32
-LINE Normal -32 64 32 64
-LINE Normal -32 32 -32 64
-LINE Normal 32 40 32 48
-LINE Normal 47 48 32 40
-TEXT 0 48 Center 0 NEG
-SYMATTR Description Inverter
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN 64 48 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 2
+Version 4
+SymbolType CELL
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+TEXT 0 48 Center 0 NEG
+SYMATTR Description Inverter
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+PINATTR PinName A
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diff --git a/CMOS/sum.asc b/CMOS/sum.asc
index eebd450..e486ed0 100644
--- a/CMOS/sum.asc
+++ b/CMOS/sum.asc
@@ -1,294 +1,294 @@
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+SYMATTR Value N-ENH
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+WINDOW 3 32 56 VTop 0
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+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
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+SYMATTR InstName V2
+SYMATTR Value -1
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+SYMATTR InstName M17
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+SYMBOL nmos 800 288 R0
+SYMATTR InstName M18
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+SYMBOL pmos 480 480 R0
+SYMATTR InstName M26
+SYMATTR Value P-ELOW
+SYMBOL nmos 1120 -160 R0
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+SYMATTR Value N-DLOW
+SYMBOL nmos 1120 288 R0
+SYMATTR InstName M22
+SYMATTR Value N-DLOW
+SYMBOL pmos 1120 32 R0
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+SYMATTR Value P-DLOW
+SYMBOL pmos 1120 480 R0
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+SYMATTR Value P-DLOW
+SYMBOL nmos 1440 -160 R0
+SYMATTR InstName M29
+SYMATTR Value N-ELOW
+SYMBOL pmos 1440 32 R0
+SYMATTR InstName M30
+SYMATTR Value P-ELOW
+SYMBOL nmos 1440 288 R0
+SYMATTR InstName M31
+SYMATTR Value N-ELOW
+SYMBOL pmos 1440 480 R0
+SYMATTR InstName M32
+SYMATTR Value P-ELOW
+TEXT -976 -336 Left 0 !.inc ./custom.mos
diff --git a/CMOS/sum.asy b/CMOS/sum.asy
index 3ad5226..4330c6e 100644
--- a/CMOS/sum.asy
+++ b/CMOS/sum.asy
@@ -1,22 +1,22 @@
-Version 4
-SymbolType CELL
-LINE Normal 48 64 32 64
-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 1 48 Center 0 SUM
-SYMATTR Description SUM gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
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+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 1 48 Center 0 SUM
+SYMATTR Description SUM gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
diff --git a/CMOS/xor.asc b/CMOS/xor.asc
index be464c6..a826306 100644
--- a/CMOS/xor.asc
+++ b/CMOS/xor.asc
@@ -1,175 +1,175 @@
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-WIRE 176 -160 176 -224
-WIRE -128 -144 -176 -144
-WIRE 128 -144 80 -144
-WIRE 464 -112 272 -112
-WIRE 1008 -112 464 -112
-WIRE 1392 -112 1008 -112
-WIRE -176 -48 -176 -144
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-WIRE 16 -48 -176 -48
-WIRE 368 -48 16 -48
-WIRE 736 -48 576 -48
-WIRE 1280 -48 1120 -48
-WIRE 80 0 80 -144
-WIRE 80 0 -272 0
-WIRE 640 0 80 0
-WIRE -80 32 -80 -64
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-WIRE 736 32 736 -48
-WIRE 1008 32 1008 -112
-WIRE 1280 32 1280 -48
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-SYMATTR Value P-ENH
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-SYMBOL nmos 128 288 R0
-SYMATTR InstName M7
-SYMATTR Value N-ENH
-SYMBOL nmos 128 480 R0
-SYMATTR InstName M8
-SYMATTR Value N-ENH
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-WINDOW 3 32 56 VTop 0
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-WINDOW 39 0 0 Left 0
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-SYMATTR Value 1
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-WINDOW 3 32 56 VTop 0
-WINDOW 123 0 0 Left 0
-WINDOW 39 0 0 Left 0
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-SYMATTR InstName M11
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-SYMBOL pmos 688 288 R0
-SYMATTR InstName M12
-SYMATTR Value P-DLOW
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-SYMATTR InstName M14
-SYMATTR Value N-DLOW
-SYMBOL pmos 960 288 R0
-SYMATTR InstName M15
-SYMATTR Value P-DLOW
-SYMBOL pmos 1232 288 R0
-SYMATTR InstName M16
-SYMATTR Value P-DLOW
-TEXT -64 -296 Left 0 !.inc ./custom.mos
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+SYMATTR InstName M7
+SYMATTR Value N-ENH
+SYMBOL nmos 128 480 R0
+SYMATTR InstName M8
+SYMATTR Value N-ENH
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+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 1
+SYMBOL voltage -336 640 R90
+WINDOW 0 -32 56 VBottom 0
+WINDOW 3 32 56 VTop 0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value -1
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+SYMATTR InstName M9
+SYMATTR Value N-DLOW
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+SYMATTR InstName M10
+SYMATTR Value N-DLOW
+SYMBOL pmos 416 288 R0
+SYMATTR InstName M11
+SYMATTR Value P-DLOW
+SYMBOL pmos 688 288 R0
+SYMATTR InstName M12
+SYMATTR Value P-DLOW
+SYMBOL standard_inverter -384 0 R0
+SYMATTR InstName X1
+SYMBOL standard_inverter -384 320 R0
+SYMATTR InstName X2
+SYMBOL nmos 960 32 R0
+SYMATTR InstName M13
+SYMATTR Value N-DLOW
+SYMBOL nmos 1232 32 R0
+SYMATTR InstName M14
+SYMATTR Value N-DLOW
+SYMBOL pmos 960 288 R0
+SYMATTR InstName M15
+SYMATTR Value P-DLOW
+SYMBOL pmos 1232 288 R0
+SYMATTR InstName M16
+SYMATTR Value P-DLOW
+TEXT -64 -296 Left 0 !.inc ./custom.mos
diff --git a/CMOS/xor.asy b/CMOS/xor.asy
index bdf30a2..c454326 100644
--- a/CMOS/xor.asy
+++ b/CMOS/xor.asy
@@ -1,22 +1,22 @@
-Version 4
-SymbolType CELL
-LINE Normal 48 64 32 64
-LINE Normal 32 64 32 56
-LINE Normal 64 64 48 64
-LINE Normal -32 48 -48 48
-LINE Normal -32 80 -48 80
-LINE Normal 32 32 -32 32
-LINE Normal 32 96 32 32
-LINE Normal -32 96 32 96
-LINE Normal -32 32 -32 96
-TEXT 1 48 Center 0 XOR
-SYMATTR Description XOR gate
-PIN -48 48 NONE 0
-PINATTR PinName A
-PINATTR SpiceOrder 1
-PIN -48 80 NONE 0
-PINATTR PinName B
-PINATTR SpiceOrder 2
-PIN 64 64 NONE 0
-PINATTR PinName Y
-PINATTR SpiceOrder 3
+Version 4
+SymbolType CELL
+LINE Normal 48 64 32 64
+LINE Normal 32 64 32 56
+LINE Normal 64 64 48 64
+LINE Normal -32 48 -48 48
+LINE Normal -32 80 -48 80
+LINE Normal 32 32 -32 32
+LINE Normal 32 96 32 32
+LINE Normal -32 96 32 96
+LINE Normal -32 32 -32 96
+TEXT 1 48 Center 0 XOR
+SYMATTR Description XOR gate
+PIN -48 48 NONE 0
+PINATTR PinName A
+PINATTR SpiceOrder 1
+PIN -48 80 NONE 0
+PINATTR PinName B
+PINATTR SpiceOrder 2
+PIN 64 64 NONE 0
+PINATTR PinName Y
+PINATTR SpiceOrder 3
author	Jed Barber <jjbarber@y7mail.com>	2016-12-15 14:26:29 +1100
committer	Jed Barber <jjbarber@y7mail.com>	2016-12-15 14:26:29 +1100
commit	76682bade38a8b2d58490ddbb80cb627a2b2ad1b (patch)
tree	2b6aa35854a5a9488e419ddf9792d4037bf697d5 /CMOS
parent	1e7286b071bcb070ddaa95f09d29614bad7a282d (diff)