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Ternary logic gate schematics
Jed Barber
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2014-02-13
Constructed simulated ternary GULLIBLE gate
Jed Barber
2014-02-13
Constructed simulated ternary CONSENSUS gate
Jed Barber
2014-02-13
Constructed simulated ternary 2 input MIN gate
Jed Barber
2014-02-13
Constructed simulated ternary 2 input MAX gate
Jed Barber
2014-02-13
Constructed simulated ternary CLAMP DOWN gate
Jed Barber
2014-02-13
Constructed simulated ternary CLAMP UP gate
Jed Barber
2014-02-13
Constructed simulated ternary buffer
Jed Barber
2014-02-13
Made symbols for all simulated ternary gates so far
Jed Barber
2014-02-13
Constructed simulated ternary IS FALSE gate
Jed Barber
2014-02-13
Constructed simulated ternary IS UNKNOWN gate
Jed Barber
2014-02-13
Constructed simulated ternary IS TRUE gate
Jed Barber
2014-02-13
Constructed simulated ternary increment gate
Jed Barber
2014-02-13
Constructed simulated ternary decrement gate
Jed Barber
2014-02-13
Constructed simulated ternary negative threshold inverter
Jed Barber
2014-02-13
Constructed simulated ternary positive threshold inverter
Jed Barber
2014-02-13
Constructed simulated ternary standard inverter
Jed Barber
2014-02-10
Added symbols for SUM and XOR gates
Jed Barber
2014-02-10
Removed placeholder sum circuit
Jed Barber
2014-02-10
Fixed references to subcircuits
Jed Barber
2014-02-10
Fixed SUM gate
Jed Barber
2014-02-10
Fixed XOR gate
Jed Barber
2014-02-03
Working, but inefficient, SUM gate constructed
Jed Barber
2014-02-02
Constructed SUM gate (not working)
Jed Barber
2014-01-31
Constructed XOR gate (not working)
Jed Barber
2014-01-31
Changed from comparison to equality and added symbol
Jed Barber
2014-01-31
Removed testing symbols and cleaned up gate layout
Jed Barber
2014-01-31
Fixed attribute problem to allow component usage in other circuits
Jed Barber
2014-01-30
Constructed comparison gate, currently not working
Jed Barber
2014-01-30
Corrected reference to renamed inverting consensus gate
Jed Barber
2014-01-30
Added gullible and inverting gullible gates
Jed Barber
2014-01-29
Changed to shorter names
Jed Barber
2014-01-29
Constructed monadic decoder gate
Jed Barber
2014-01-29
Changed names to match symbols
Jed Barber
2014-01-29
Fixed component references
Jed Barber
2014-01-29
Cleaned up symbol attribute details
Jed Barber
2014-01-29
Constructed consensus gate
Jed Barber
2014-01-29
Modified circuits to match symbols
Jed Barber
2014-01-29
Added symbol for consensus gate
Jed Barber
2014-01-29
Added symbol for inverting consensus gate
Jed Barber
2014-01-29
Constructed inverting consensus gate
Jed Barber
2014-01-29
Constructed MIN gate
Jed Barber
2014-01-29
Constructed MAX gate
Jed Barber
2014-01-29
Changed names of circuits to match their symbols
Jed Barber
2014-01-29
Added symbol for CLAMP DOWN gate
Jed Barber
2014-01-29
Added symbol for CLAMP UP gate
Jed Barber
2014-01-29
Added symbol for BUFFER gate
Jed Barber
2014-01-29
Added symbol for INCREMENT gate
Jed Barber
2014-01-29
Added symbol for DECREMENT gate
Jed Barber
2014-01-29
Added symbol for IS UNKNOWN gate
Jed Barber
2014-01-29
Added symbol for IS TRUE gate
Jed Barber
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