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Ternary logic gate schematics
Jed Barber
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2014-01-29
Added symbol for CLAMP DOWN gate
Jed Barber
2014-01-29
Added symbol for CLAMP UP gate
Jed Barber
2014-01-29
Added symbol for BUFFER gate
Jed Barber
2014-01-29
Added symbol for INCREMENT gate
Jed Barber
2014-01-29
Added symbol for DECREMENT gate
Jed Barber
2014-01-29
Added symbol for IS UNKNOWN gate
Jed Barber
2014-01-29
Added symbol for IS TRUE gate
Jed Barber
2014-01-29
Added symbol for IS FALSE gate
Jed Barber
2014-01-29
Modified circuits to match up to their corresponding symbols
Jed Barber
2014-01-29
Fixed symbols to signify that they aren't inverting
Jed Barber
2014-01-29
Added symbol for STI gate
Jed Barber
2014-01-29
Added symbol for PTI gate
Jed Barber
2014-01-29
Added symbol for NTI gate
Jed Barber
2014-01-29
Added symbol for 2 input ANTIMIN gate
Jed Barber
2014-01-29
Added symbol for 2 input ANTIMAX gate
Jed Barber
2014-01-29
Added symbol for 2 input MIN gate
Jed Barber
2014-01-29
Added symbol for 2 input MAX gate
Jed Barber
2014-01-29
Completed decrement circuit
Jed Barber
2014-01-28
Completed increment circuit
Jed Barber
2014-01-28
Added another LTspice simulation file
Jed Barber
2014-01-28
Fixed include statements
Jed Barber
2014-01-28
Models for CMOS custom mosfets
Jed Barber
2014-01-28
Ignore files generated by LTspice simulations
Jed Barber
2014-01-28
Circuits already constructed
Jed Barber
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