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AgeCommit message (Expand)Author
2014-03-01Corrected transistor countJed Barber
2014-02-14Fixed symbols that shouldn't indicate inversionJed Barber
2014-02-14Added symbols for the rest of the gatesJed Barber
2014-02-14Constructed simulated ternary SUM gateJed Barber
2014-02-14Constructed simulated ternary XOR gateJed Barber
2014-02-14Constructed simulated ternary EQUALITY gateJed Barber
2014-02-13Removed superfluous ground connections to AND/OR/NOT gatesJed Barber
2014-02-13Constructed simulated ternary GULLIBLE gateJed Barber
2014-02-13Constructed simulated ternary CONSENSUS gateJed Barber
2014-02-13Constructed simulated ternary 2 input MIN gateJed Barber
2014-02-13Constructed simulated ternary 2 input MAX gateJed Barber
2014-02-13Constructed simulated ternary CLAMP DOWN gateJed Barber
2014-02-13Constructed simulated ternary CLAMP UP gateJed Barber
2014-02-13Constructed simulated ternary bufferJed Barber
2014-02-13Made symbols for all simulated ternary gates so farJed Barber
2014-02-13Constructed simulated ternary IS FALSE gateJed Barber
2014-02-13Constructed simulated ternary IS UNKNOWN gateJed Barber
2014-02-13Constructed simulated ternary IS TRUE gateJed Barber
2014-02-13Constructed simulated ternary increment gateJed Barber
2014-02-13Constructed simulated ternary decrement gateJed Barber
2014-02-13Constructed simulated ternary negative threshold inverterJed Barber
2014-02-13Constructed simulated ternary positive threshold inverterJed Barber
2014-02-13Constructed simulated ternary standard inverterJed Barber
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