Age | Commit message (Expand) | Author |
2014-03-01 | Corrected transistor count | Jed Barber |
2014-02-14 | Fixed symbols that shouldn't indicate inversion | Jed Barber |
2014-02-14 | Added symbols for the rest of the gates | Jed Barber |
2014-02-14 | Constructed simulated ternary SUM gate | Jed Barber |
2014-02-14 | Constructed simulated ternary XOR gate | Jed Barber |
2014-02-14 | Constructed simulated ternary EQUALITY gate | Jed Barber |
2014-02-13 | Removed superfluous ground connections to AND/OR/NOT gates | Jed Barber |
2014-02-13 | Constructed simulated ternary GULLIBLE gate | Jed Barber |
2014-02-13 | Constructed simulated ternary CONSENSUS gate | Jed Barber |
2014-02-13 | Constructed simulated ternary 2 input MIN gate | Jed Barber |
2014-02-13 | Constructed simulated ternary 2 input MAX gate | Jed Barber |
2014-02-13 | Constructed simulated ternary CLAMP DOWN gate | Jed Barber |
2014-02-13 | Constructed simulated ternary CLAMP UP gate | Jed Barber |
2014-02-13 | Constructed simulated ternary buffer | Jed Barber |
2014-02-13 | Made symbols for all simulated ternary gates so far | Jed Barber |
2014-02-13 | Constructed simulated ternary IS FALSE gate | Jed Barber |
2014-02-13 | Constructed simulated ternary IS UNKNOWN gate | Jed Barber |
2014-02-13 | Constructed simulated ternary IS TRUE gate | Jed Barber |
2014-02-13 | Constructed simulated ternary increment gate | Jed Barber |
2014-02-13 | Constructed simulated ternary decrement gate | Jed Barber |
2014-02-13 | Constructed simulated ternary negative threshold inverter | Jed Barber |
2014-02-13 | Constructed simulated ternary positive threshold inverter | Jed Barber |
2014-02-13 | Constructed simulated ternary standard inverter | Jed Barber |