Age | Commit message (Expand) | Author |
2014-03-01 | Corrected transistor count | Jed Barber |
2014-02-28 | Removed unuseful symbols | Jed Barber |
2014-02-28 | Constructed CONS, GULL, MAX, MIN gates | Jed Barber |
2014-02-28 | Constructed RMOS INC, DEC, inverting CONS gates | Jed Barber |
2014-02-26 | Constructed RMOS buffer, IS gates | Jed Barber |
2014-02-26 | Added symbols (copies of the CMOS symbols) | Jed Barber |
2014-02-26 | Removed test voltages, added input/output labels | Jed Barber |
2014-02-26 | Added RMOS clamps, threshold inverters | Jed Barber |
2014-02-25 | Updated readme to note different RMOS methods | Jed Barber |
2014-02-25 | Constructed ANTIMAX gate in RMOS | Jed Barber |
2014-02-25 | Modified existing gates to use custom mosfets | Jed Barber |
2014-02-25 | Added custom mosfet file for RMOS | Jed Barber |
2014-02-20 | Added readme | Jed Barber |
2014-02-14 | Fixed symbols that shouldn't indicate inversion | Jed Barber |
2014-02-14 | Added symbols for the rest of the gates | Jed Barber |
2014-02-14 | Constructed simulated ternary SUM gate | Jed Barber |
2014-02-14 | Constructed simulated ternary XOR gate | Jed Barber |
2014-02-14 | Constructed simulated ternary EQUALITY gate | Jed Barber |
2014-02-13 | Removed superfluous ground connections to AND/OR/NOT gates | Jed Barber |
2014-02-13 | Constructed simulated ternary GULLIBLE gate | Jed Barber |
2014-02-13 | Constructed simulated ternary CONSENSUS gate | Jed Barber |
2014-02-13 | Constructed simulated ternary 2 input MIN gate | Jed Barber |
2014-02-13 | Constructed simulated ternary 2 input MAX gate | Jed Barber |
2014-02-13 | Constructed simulated ternary CLAMP DOWN gate | Jed Barber |
2014-02-13 | Constructed simulated ternary CLAMP UP gate | Jed Barber |
2014-02-13 | Constructed simulated ternary buffer | Jed Barber |
2014-02-13 | Made symbols for all simulated ternary gates so far | Jed Barber |
2014-02-13 | Constructed simulated ternary IS FALSE gate | Jed Barber |
2014-02-13 | Constructed simulated ternary IS UNKNOWN gate | Jed Barber |
2014-02-13 | Constructed simulated ternary IS TRUE gate | Jed Barber |
2014-02-13 | Constructed simulated ternary increment gate | Jed Barber |
2014-02-13 | Constructed simulated ternary decrement gate | Jed Barber |
2014-02-13 | Constructed simulated ternary negative threshold inverter | Jed Barber |
2014-02-13 | Constructed simulated ternary positive threshold inverter | Jed Barber |
2014-02-13 | Constructed simulated ternary standard inverter | Jed Barber |
2014-02-10 | Added symbols for SUM and XOR gates | Jed Barber |
2014-02-10 | Removed placeholder sum circuit | Jed Barber |
2014-02-10 | Fixed references to subcircuits | Jed Barber |
2014-02-10 | Fixed SUM gate | Jed Barber |
2014-02-10 | Fixed XOR gate | Jed Barber |
2014-02-03 | Working, but inefficient, SUM gate constructed | Jed Barber |
2014-02-02 | Constructed SUM gate (not working) | Jed Barber |
2014-01-31 | Constructed XOR gate (not working) | Jed Barber |
2014-01-31 | Changed from comparison to equality and added symbol | Jed Barber |
2014-01-31 | Removed testing symbols and cleaned up gate layout | Jed Barber |
2014-01-31 | Fixed attribute problem to allow component usage in other circuits | Jed Barber |
2014-01-30 | Constructed comparison gate, currently not working | Jed Barber |
2014-01-30 | Corrected reference to renamed inverting consensus gate | Jed Barber |
2014-01-30 | Added gullible and inverting gullible gates | Jed Barber |
2014-01-29 | Changed to shorter names | Jed Barber |