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AgeCommit message (Collapse)Author
2016-12-15Old uncommitted changesHEADmasterJed Barber
2014-04-23Remaining ternary gate symbols addedJed Barber
2014-04-23Added all remaining monadic gate symbols except clampsJed Barber
2014-04-22Added pins to STI and added symbols for NTI, PTIJed Barber
2014-04-22Added inverter symbol to tinyCAD libraryJed Barber
2014-04-20Positive/negative threshold inverter schematicsJed Barber
2014-04-16Schematic of inverter for publishingJed Barber
2014-03-20Essentially public domainJed Barber
2014-03-02Constructed 3-input ANTIMAX, ANTIMIN gatesJed Barber
2014-03-02Updated readmeJed Barber
2014-03-01Constructed RMOS EQUALITY, SUM, XOR gatesJed Barber
2014-03-01Corrected transistor countJed Barber
2014-02-28Removed unuseful symbolsJed Barber
2014-02-28Constructed CONS, GULL, MAX, MIN gatesJed Barber
2014-02-28Constructed RMOS INC, DEC, inverting CONS gatesJed Barber
2014-02-26Constructed RMOS buffer, IS gatesJed Barber
2014-02-26Added symbols (copies of the CMOS symbols)Jed Barber
2014-02-26Removed test voltages, added input/output labelsJed Barber
2014-02-26Added RMOS clamps, threshold invertersJed Barber
2014-02-25Updated readme to note different RMOS methodsJed Barber
2014-02-25Constructed ANTIMAX gate in RMOSJed Barber
2014-02-25Modified existing gates to use custom mosfetsJed Barber
2014-02-25Added custom mosfet file for RMOSJed Barber
2014-02-20Added readmeJed Barber
2014-02-14Fixed symbols that shouldn't indicate inversionJed Barber
2014-02-14Added symbols for the rest of the gatesJed Barber
2014-02-14Constructed simulated ternary SUM gateJed Barber
2014-02-14Constructed simulated ternary XOR gateJed Barber
2014-02-14Constructed simulated ternary EQUALITY gateJed Barber
2014-02-13Removed superfluous ground connections to AND/OR/NOT gatesJed Barber
2014-02-13Constructed simulated ternary GULLIBLE gateJed Barber
2014-02-13Constructed simulated ternary CONSENSUS gateJed Barber
2014-02-13Constructed simulated ternary 2 input MIN gateJed Barber
2014-02-13Constructed simulated ternary 2 input MAX gateJed Barber
2014-02-13Constructed simulated ternary CLAMP DOWN gateJed Barber
2014-02-13Constructed simulated ternary CLAMP UP gateJed Barber
2014-02-13Constructed simulated ternary bufferJed Barber
2014-02-13Made symbols for all simulated ternary gates so farJed Barber
2014-02-13Constructed simulated ternary IS FALSE gateJed Barber
2014-02-13Constructed simulated ternary IS UNKNOWN gateJed Barber
2014-02-13Constructed simulated ternary IS TRUE gateJed Barber
2014-02-13Constructed simulated ternary increment gateJed Barber
2014-02-13Constructed simulated ternary decrement gateJed Barber
2014-02-13Constructed simulated ternary negative threshold inverterJed Barber
2014-02-13Constructed simulated ternary positive threshold inverterJed Barber
2014-02-13Constructed simulated ternary standard inverterJed Barber
2014-02-10Added symbols for SUM and XOR gatesJed Barber
2014-02-10Removed placeholder sum circuitJed Barber
2014-02-10Fixed references to subcircuitsJed Barber
2014-02-10Fixed SUM gateJed Barber
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